pin description

1      inv    inverting input of the error amplifier. the information on the output voltage of the pfc preregulator
              is fed into the pin through a resistor divider.

2      comp   output of the error amplifier. a compensation network is placed between this pin and inv (pin
              #1) to achieve stability of the voltage control loop and ensure high power factor and low thd.

3      mult   main input to the multiplier. this pin is connected to the rectified mains voltage via a resistor
              divider and provides the sinusoidal reference to the current loop.

4      cs     input to the pwm comparator. the current flowing in the mosfet is sensed through a resistor,
              the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped
              reference, generated by the multiplier, to determine mosfet’s turn-off.

5      zcd    boost inductor’s demagnetization sensing input for transition-mode operation. a negative-going
              edge triggers mosfet’s turn-on.

6      gnd    ground. current return for both the signal part of the ic and the gate driver.

7      gd     gate driver output. the totem pole output stage is able to drive power mosfet’s and igbt’s
              with a peak current of 600 ma source and 800 ma sink. the high-level voltage of this pin is
              clamped at about 12v to avoid excessive gate voltages in case the pin is supplied with a high
              vcc.

8      vcc    supply voltage of both the signal part of the ic and the gate driver. the supply voltage upper
              limit is extended to 22v min. to provide more headroom for supply voltage changes.

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