- high speed: tpd= 3.8ns (typ) at vcc= 5v
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- low power dissipation: icc= 1µa (max) at ta= 25°c
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- ttl-compatible inputs: vil= 0.8v; vih= 2.0v
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- cmos-compatible outputs: voh> 0.8vcc; vol< 0.1vcc@load
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- power down protection provided on inputs and outputs
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- balanced propagation delays
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- pin and function compatible with other standard logic families
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- chip complexity: fets = 105; equivalent gates = 26
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- pb-free packages are available
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