全新原裝、現貨
features
• double-data-rate architecture; two data transfers per
clock cycle 
• the high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
• bi-directional data strobe (dqs) is transmitted
/received with data for capturing data at the receiver
• data inputs, outputs, and dm are synchronized with
dqs
• dqs is edge-aligned with data for reads; center-
aligned with data for writes
• differential clock inputs (ck and /ck)
• dll aligns dq and dqs transitions with ck
transitions
• commands entered on each positive ck edge; data
and data mask referenced to both edges of dqs
• data mask (dm) for write data

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