74hc125d     ---74hc/hct125

quad buffer/line driver; 3-state

features
· output capability: bus driver
· icc category: msi
general description
the 74hc/hct125 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl).
they are specified in compliance with jedec standard no. 7a.
the 74hc/hct125 are four non-inverting buffer/line drivers with 3-state outputs. the 3-state outputs (ny) are controlled
by the output enable input (noe). a high at noe causes the outputs to assume a high impedance off-state.
the “125” is identical to the “126” but has active low enable inputs.
quick reference data
gnd = 0 v; tamb = 25 °c; tr = tf = 6 ns

quick reference data
gnd = 0 v; tamb = 25 °c; tr = tf = 6 ns
notes
1. cpd is used to determine the dynamic power dissipation (pd in mw):
pd = cpd ´ vcc
2 ´ fi + å (cl ´ vcc
2 ´ fo) where:
fi = input frequency in mhz
fo = output frequency in mhz
cl = output load capacitance in pf
vcc = supply voltage in v
å (cl ´ vcc
2 ´ fo) = sum of outputs
2. for hc the condition is vi = gnd to vcc
for hct the condition is vi = gnd to vcc - 1.5 v
ordering information
see “74hc/hct/hcu/hcmos logic package information”.
symbol parameter conditions
typical
unit
hc hct
tphl/ tplh propagation delay na to ny cl = 15 pf; vcc = 5 v 9 12 ns
ci input capacitance 3.5 3.5 pf
cpd power dissipation capacitance per buffer notes 1 and 2 22 24 pf