8 bit shift register with output latches (3 state)

.high speed
.fmax = 55 mhz (typ.) at vcc = 5 v lowpower dissipation
.icc = 4 ma (max.) at ta = 25 °c high noise immunity
.vnih = vnil = 28 % vcc (min.) output drive capability
15 lsttl loads for qa to qh
.10 lsttl loads for qh’ symmetrical output impedance
|ioh| = iol = 6 ma (min.) for qa toqh
.|ioh| = iol = 4 ma (min.) for qh’ balancedpropagation delays
.tplh = tphl wide operating voltage range
.vcc (opr) = 2 v to 6 v pin and function compatible
with lsttl 54/74ls595