2 features
cpu configuration
• 1k×13 bits on chip rom
• 32×8 bits on-chip registers (sram, 
general purpose)
• 5 level stacks for subroutine nesting 
• less than 1.5 ma at 5v/4mhz
• typically 15 μa, at 3v/32khz
• typically 1 μa, during sleep mode
i/o port configuration
• 2 bidirectional i/o ports : p5, p6
• 12 i/o pins
• wake-up port : p6
• 6 programmable pull-down i/o pins
• 7 programmable pull-high i/o pins
• 7 programmable open-drain i/o pins
• external interrupt : p60
operating voltage range:
• otp version: 2.3v~5.5v operating voltage range: 
operating temperature range: 0~70°c
operating frequency range (base on 2 clocks):
• crystal mode:
dc~20mhz/2clks @ 5v; dc~100ns inst. cycle @ 5v
dc~8mhz/2clks @ 3v; dc~250ns inst. cycle @ 3v
dc~4mhz/2clks @ 2.3v; dc~500ns inst. cycle @ 2.3v
• erc mode:
dc~4 mhz/2clks @ 5v; dc~500ns inst. cycle @ 5v
dc~4 mhz/2clks @ 3v; dc~500ns inst. cycle @ 3v
dc~4 mhz/2clks @ 2.3v; dc~500ns inst. cycle @ 2.3v
• irc mode: 
  peripheral configuration
• 8-bit real time clock/counter (tcc) with
selective signal sources, trigger edges,
and overflow interrupt 
three available interrupts:
• tcc overflow interrupt
• input-port status changed interrupt
(wake-up from sleep mode)
• external interrupt  
special features
• programmable free running watchdog
timer 
• power saving sleep mode
• selectable oscillation mode 
other features
• programmable prescaler of oscillator
set-up time
• one security register to prevent intrusion
of user’s otp memory code
• one configuration register to match
user’s requirement
two clocks per instruction cycle
package type:
• 14-pin dip 300mil : em78p153sp/s/j
• 14-pin sop 150mil : em78p153sn/s/j
• 10-pin ssop 150mil : em78p152sn/s/j
note: these are all green products
which do not contain hazardous 
substances.