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參數資料
| 型號： | 552CK000230DG |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, CMOS OUTPUT |
| 封裝： | ROHS COMPLIANT PACKAGE-6 |
| 文件頁數： | 7/14頁 |
| 文件大小： | 236K |
| 代理商： | 552CK000230DG |
Si552
2
Rev. 0.6
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Supply Voltage1
VDD
3.3 V option
2.97
3.3
3.63
V
2.5 V option
2.25
2.5
2.75
1.8 V option
1.71
1.8
1.89
Supply Current
IDD
Output enabled
LVPECL
CML
LVDS
CMOS
—
120
108
99
90
130
117
108
98
mA
Tristate mode
—
60
75
Frequency Select (FS)2
VIH
0.75 x VDD
——
V
VIL
——
0.5
Operating Temperature Range
TA
–40
—
85
C
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 8 for further details.
2. FS pin includes a 17 k
resistor to VDD.
Table 2. VC Control Voltage Input
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Control Voltage Tuning Slope1,2,3
KV
10 to 90% of VDD
—33
45
90
135
180
356
—
ppm/V
Control Voltage Linearity4
LVC
BSL
–5
±1
+5
%
Incremental
–10
±5
+10
Modulation Bandwidth
BW
9.3
10.0
10.7
kHz
VC Input Impedance
ZVC
500
—
k
Nominal Control Voltage
VCNOM
@ fO
—VDD/2
—
V
Control Voltage Tuning Range
VC
0VDD
V
Notes:
1. Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 8.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD.
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