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參數資料
型號: 88C25-AF5-R
廠商: 友順科技股份有限公司
英文描述: BUILT-IN DELAY CIRCUIT HIGH-PRECISION VOLTAGE DETECTOR
中文描述: 內置延遲電路高精度電壓檢測器
文件頁數: 16/16頁
文件大小: 227K
代理商: 88C25-AF5-R
88CXX
CMOS IC
UNISONICTECHNOLOGIESCO.,LTD
9
www.unisonic.com.tw
QW-R502-040,A
OPERATION
1. Basic operation: CMOS active low output
(1) When power supply voltage VDD is greater than the release voltage +VDET, the Nch transistor is OFF and the
Pch transistor ON, causing VDD (high) to appear at the output.
(2) When power supply voltage VDD goes below +VDET, the output maintains the power supply voltage level, as
long as VDD remains above the detection voltage -VDET. When VDD does fall below -VDET (A in Figure 7), the Nch
transistor goes ON the Pch transistor goes OFF, and VSS appears at the output.
(3) When VDD falls below the minimum operating voltage, the output becomes undefined. However, output will
revert to VDD if a pull-up has been employed.
(4) VSS will again be output when VDD rises above the minimum operating voltage. VSS will continue to be output
even when VDD surpasses -VDET, as long as it does not exceed the release voltage +VDET.
(5) When VDD rises above +VDET (B in Figure 7), the Nch transistor goes OFF the Pch transistor goes ON, and VDD
appears at the output. Then VDD at the OUT terminal appears with delay time (td) due to delay circuit.
*Parasitic diode
VREF
*
CD
OUT
Delay
circuit
*
N
RC
RB
RA
+
-
CD
Nch
Pch
Figure 6
A
B
Hysteresis
width(VHYS)
Release voltage (+VDET)
Detection voltage (-VDET)
Min.operating voltage
Vss
OUT terminal output
VDD
Vss
td
Figure 7
(1)
(2)
(3)
(4)
(5)
VDD
Vss
VDD
2. Delay circuit
The delay circuit outputs the signal delayed from the release voltage (+VDET) point of the power voltage VDD
rising. The output signal is not delayed when the VDD goes down the detection voltage (-VDET) or less. (See Figure 7).
The delay time (td) is determined by the time constant of the built-in constant current (approx. 100nA in the case
of products with detection voltage of 1.5V or more, approx. 570nA in the case of products with detection voltage of
1.4V or less) and the attached external capacitor (CD), and calculated from the following formula.
td (ms) = Delay factor×CD (nF)
Delay factor: (25 )
Products with detection voltage of 1.4V or less: Min.0.57, Typ.0.77, Max.0.96
Products with detection voltage of 1.5V or more: Min.3.8, Typ. 5.1, Max.6.4
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