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參數資料
| 型號： | 935212880551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, SOT-307, QFP-44 |
| 文件頁數： | 27/67頁 |
| 文件大小： | 356K |
| 代理商： | 935212880551 |
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1997 Nov 17
33
Philips Semiconductors
Preliminary specication
ISO/MPEG Audio Source Decoder
SAA2502
Table 24 Explanation of bits in Table 23
Notes
1. DST0 values in general do not have a determined duration. However, DST0 = logic 1 lasts at least 0.4 frame period
when MPEG layer I data is decoded, and 0.8 frame period when MPEG layer II data is decoded. Table 25 indicates
the validity of the SAA2502 readable data items with respect to the decoding subprocess.
2. Some of the readable local register bits only have significance if INSYNC is logic 1.
Table 25 Validity of the SAA2502 readable data items with respect to the decoding subprocess
Note
1. Reading of a data item in a period when it is not valid renders undefined data
7.6.6.2
Clock generator control
Table 26 Clock generator control 1: 1 byte (write-only, unrestricted type, local address = 11H)
Table 27 Clock generator control 2: 1 byte (write-only, unrestricted type, local address = 12H)
BIT
DESCRIPTION
DST1 and DST0
By interpreting DST1 and 0, the host can synchronize to the input frame frequency and
also determine at which moment specific data items are available to be read. The value
of DST1 and 0 is only valid if flag INSYNC is set.
DST1
This is a modulo 2 frame counter, i.e. DST1 inverts at the moment the decoding of a
new frame is started. DST1 enables the host to sample the data items available flag
DST0 less frequently, meanwhile enabling the host to see if it missed a state.
DST0
Bit indicates whether data items are available to be read; note 1:
logic 0 indicates updating of data items is in progress (consequently they are invalid)
logic 1 indicates ancillary (or PAD) data, frame headers and error report are valid.
INSYNC
Synchronization indication:
logic 0 indicates not synchronized to input audio frame borders
logic 1 indicates synchronized to input audio frame borders; note 2.
DECODING FRAME n
DECODING FRAME n + 1
DST1 = 0
DST1 = 1
DST0 = 0
DST0 = 1
DST0 = 0
DST0 = 1
Not valid; note 1
ancillary data (frame n
1)
not valid; note 1
ancillary data (frame n)
frame headers (frame n)
frame headers (framen+1)
error report (frame n)
error report (frame n+1)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FSCINP
FSC384
FSCENA
N3b4
N3b3
N3b2
N3b1
N3b0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
N2b1
N2b0
N1b3
N1b2
N1b1
N1b0
PHSRVS
PHSMOD
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