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參數資料
| 型號： | 951901AF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 133.34 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, GREEN, MO-118, SSOP-48 |
| 文件頁數： | 16/21頁 |
| 文件大小： | 206K |
| 代理商： | 951901AF |
4
ICS951901
0670B—07/15/04
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
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B-
1
d
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v
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e
R
6
t
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B-
1
d
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v
r
e
s
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R
5
t
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B3
11
4
K
L
C
I
C
P
4
t
i
B2
11
3
K
L
C
I
C
P
3
t
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B1
11
2
K
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C
I
C
P
2
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11
1
K
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1
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B9
1
0
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0
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Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
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B#
N
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PD
W
PN
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7
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6
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B1
21
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4
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5
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B0
21
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8
4
t
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B6
21
2
1
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3
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B7
21
1
M
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2
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B8
21
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1
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1
t
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B0
31
9
M
A
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D
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0
t
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B1
31
8
M
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D
S
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
T
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B#
N
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P
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2
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5
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1
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A
0
t
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B6
11
0
K
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C
P
G
A
Byte 5: AGP, Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
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P
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C
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7
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31
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6
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31
6
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5
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31
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4
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5
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