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參數資料
| 型號： | 992215735051 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CPGA76 |
| 封裝： | PGA-76 |
| 文件頁數： | 7/17頁 |
| 文件大小： | 171K |
| 代理商： | 992215735051 |
1999 September
15
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Pin configuration
The FTT1010-M is mounted in a Pin Grid Array (PGA) package with
76 pins in a 15x13 grid of 40.00 x 40.00 mm2. The position of pin A1
is marked with a gold dot on top of the package.
Figure 13 - FTT1010-M pin configuration (top view)
Symbol
Name
Pin # W
Pin # X
Pin # Y
Pin # Z
VNS
VPS
SFD
SFS
VCS
OG
RD
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
SG
RG
OUT
NC
N substrate
P substrate
Source Follower Drain
Source Follower Source
Current Source
Output Gate
Reset Drain
Image Clock (Phase 1)
Image Clock (Phase 2)
Image Clock (Phase 3)
Image Clock (Phase 4)
Storage Clock (Phase 1)
Storage Clock (Phase 2)
Storage Clock (Phase 3)
Storage Clock (Phase 4)
Register Clock (Phase 1)
Register Clock (Phase 2)
Register Clock (Phase 3)
Summing Gate
Reset Gate
Output
Not connected
A12
D11
E11
E12
-
C11
A13
A10
A11
B13
B12
-
D13
C12
D12
C13
B9
B8
A8
B10
A9
B11
B7
A3
B2
D3
E2
E3
C3
A1
B5
A4
B1
B3
-
D1
C2
D2
C1
A6
A7
B6
A2
A5
B4
J2
F3
-
G3
J1
J4
J3
H1
H2
F1
G2
F2
G1
-
H5
H6
J6
H4
J5
H3
H7
F11
H12
J11
-
G11
J13
H9
J10
H13
H11
F13
G12
F12
G13
-
J8
J7
H8
J12
J9
H10
The clock phases of quadrant W are internally connected to X, and
the clock phases of Y are connected to Z.
J
H
G
F
E
D
C
B
A
J
H
G
F
E
D
C
B
A
SFD
VNS
VCS
SFS
RG
C2
C3
OG
RD
OUT
SG
C1
C2
NC
A4
A2
VPS
A1
A3
VNS
A4
A2
VPS
A1
A3
VNS
SFD
VNS
VCS
SFS
RG
C3
OG
RD
OUT
SG
C1
VNS
SFD
VNS
VCS
SFS
RG
C3
OG
RD
OUT
SG
C1
C2
VPS
VNS
B4
B2
VPS
B1
B3
VNS
SFD
NC
VCS
SFS
RG
C3
OG
RD
OUT
SG
C1
VNS
B4
B2
B1
B3
VNS
C2
VNS
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
4
5
6
7
8
9
10
11
12
13
B4
B1
B4
B1
IMAGE
TOP
Y
Z
X
W
FTT1010-M
STORAGE
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