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參數(shù)資料
| 型號： | AD7724AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Dual CMOS Modulators |
| 中文描述： | 2-CH 1-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大小： | 552K |
| 代理商： | AD7724AST |
REV. A
–2–
AD7724–SPECIFICATIONS
1
(AVDD = 5 V
6
5%; DVDD = 5 V
6
5%, DVDD1 = 3 V
6
5%; AGND = DGND = 0 V,
f
MCLK
= 13 MHz ac-coupled sine wave, REF2A = REF2B=2.5 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Parameter
A Version
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Integral Nonlinearity
Offset Error
Gain Error
2
Offset Error Drift
Gain Error Drift
Unipolar Mode
Bipolar Mode
When Tested with Ideal FIR Filter as in Figure 1
±
0.003
±
0.24
±
0.6
±
37.69
% FSR typ
% FSR typ
% FSR typ
μ
V/
°
C typ
REF2 Is an Ideal Reference, REF1 = AGND
±
37.69
±
18.85
μ
V/
°
C typ
μ
V/
°
C typ
ANALOG INPUTS
Signal Input Span (VIN(+) – VIN(–))
Bipolar Mode
Unipolar Mode
Maximum Input Voltage
Minimum Input Voltage
Input Sampling Capacitance
Input Sampling Rate
Differential Input Impedance
±
V
REF2
/2
0 to V
REF2
AVDD
0
2
2 f
MCLK
10
9
/(8 f
MCLK
)
V max
V max
V
V
pF typ
MHz
k
typ
BIP = V
IH
BIP = V
IL
REFERENCE INPUTS
REF1 Output Voltage
REF1 Output Voltage Drift
REF1 Output Impedance
Reference Buffer Offset Voltage
Using Internal Reference
REF2 Output Voltage
REF2 Output Voltage Drift
Using External Reference
REF2 Input Impedance
External Reference Voltage Range
DYNAMIC SPECIFICATIONS
3
Bipolar Mode
2.32 to 2.68
60
4
±
12
V min/max
ppm/
°
C typ
k
typ
mV max
Offset Between REF1 and REF2
2.32 to 2.68
60
V min/max
ppm/
°
C typ
REF1 = AGND
10
9
/(16 f
MCLK
)
2.32 to 2.68
k
typ
V min/max
Applied to REF1 or REF2
When Tested with Ideal FIR Filter as in Figure 1
BIP = V
IH
, V
CM
= 2.5 V, VIN(+) = VIN(–) = 1.25 V p-p
or VIN(–) = 1.25 V, VIN(+) = 0 V to 2.5 V
Input BW = 0 kHz–94.25 kHz
Signal-to-(Noise + Distortion)
90
86
–90
–90
dB typ
dB min
dB max
dB max
Total Harmonic Distortion
Spurious Free Dynamic Range
Unipolar Mode
Signal-to-(Noise + Distortion)
Total Harmonic Distortion
Spurious Free Dynamic Range
Intermodulation Distortion
AC CMRR
Input BW = 0 kHz–94.25 kHz
Input BW = 0 kHz–94.25 kHz
BIP = V
IL
, VIN(–) = 0 V, VIN(+) = 0 V to 2.5 V
Input BW = 0 kHz–94.25 kHz
Input BW = 0 kHz–101.556 kHz
Input BW = 0 kHz–101.556 kHz
88
–90
–90
–93
96
dB typ
dB typ
dB typ
dB typ
dB typ
VIN(+) = VIN(–) = 2.5 V p-p, V
CM
= 1.25 V to
3.75 V, 20 kHz
CLOCK
Square Wave
4
MCLK Duty Ratio
V
MCLKH
, MCLK High Voltage
V
MCLKL
, MCLK Low Voltage
Sine Wave
XTAL1 Voltage Swing
45 to 55
4
0.4
% max
V min
V max
For Specified Operation
MCLK Uses CMOS Logic
0.4
4
V p-p min
V p-p max
XTAL_OFF Tied Low
LOGIC INPUTS
V
IH
, Input High Voltage
V
IL
, Input Low Voltage
I
INH
, Input Current
C
IN
, Input Capacitance
2.4
0.8
10
10
V min
V max
μ
A max
pF max
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