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參數資料
| 型號： | AD7730 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 橋傳感器模數轉換器 |
| 文件頁數： | 36/52頁 |
| 文件大小： | 497K |
| 代理商： | AD7730 |
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AD7730/AD7730L
–36–
REV. A
In DSP applications, the SCLK is generally a continuous clock.
In these applications, the
CS
input for the AD7730 is generated
from a frame synchronization signal from the DSP. In these
applications, the first edge after
CS
goes low is the active edge.
T he MSB of the data to be shifted into the DSP must be set up
prior to this first active edge. Unlike microcontroller applica-
tions, the DSP does not provide a clock edge to clock the MSB
from the AD7730. In this case, the
CS
of the AD7730 places
the MSB on the DOUT line. For processors with the rising edge
of SCLK as the active edge, the POL input should be tied high.
In this case, the DSP takes data on the rising edge. If
CS
goes
low while SCLK is low, the MSB is clocked out on the DOUT
line from the
CS
. Subsequent data bits are clocked from the
falling edge of SCLK . For processors with the falling edge of
SCLK as the active edge, the POL input should be tied low. In
this case, the DSP takes data on the falling edge. If
CS
goes low
while SCLK is high, the MSB is clocked out on the DOUT line
from the
CS
. Subsequent data bits are clocked from the rising
edge of SCLK .
Figure 18. Read Cycle Timing Diagram
Figure 19. Write Cycle Timing Diagram
T he
RDY
line is used as a status signal to indicate when data is
ready to be read from the AD7730’s data register.
RDY
goes
low when a new data word is available in the data register. It is
reset high when a read operation from the data register is com-
plete. It also goes high prior to the updating of the data register
to indicate when a read from the data register should not be
initiated. T his is to ensure that the transfer of data from the data
register to the output shift register does not occur while the data
register is being updated. It is possible to read the same data
twice from the output register even though the
RDY
line returns
high after the first read operation. Care must be taken, however,
to ensure that the read operations are not initiated as the next
output update is about to take place.
For systems with a single data line, the DIN and DOUT lines
on the AD7730 can be connected together, but care must be
taken in this case not to place the part in continuous read mode
as the part monitors DIN while supplying data on DOUT and
as a result, it may not be possible to take the part out of its
continuous read mode.
DOUT
SCLK
(POL = 1)
CS
RDY
MSB
t
5
t
7
t
9
LSB
t
8
t
6
t
4
t
3
t
10
SCLK
(POL = 0)
t
5A
t
6
t
7
DIN
SCLK
(POL = 1)
CS
MSB
t
12
t
15
LSB
t
16
t
14
t
11
t
13
SCLK
(POL = 0)
t
14
t
15
相關PDF資料 |
PDF描述 |
|---|---|
| AD7730BN | Bridge Transducer ADC |
| AD7730BR | Bridge Transducer ADC |
| AD7730BRU | Bridge Transducer ADC |
| AD7730L | Bridge Transducer ADC |
| AD7731 | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7730_12 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Bridge Transducer ADC |
| AD7730BN | 功能描述:IC ADC TRANSDUCER BRIDGE 24-DIP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BNZ | 功能描述:IC ADC TRANSDUCER BRIDGE 24-DIP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BR | 功能描述:IC ADC BRIDGE TRANSDUCER 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BR-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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