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參數資料
型號: AD7750
廠商: Analog Devices, Inc.
英文描述: Product-to-Frequency Converter(乘積-頻率轉換器)
中文描述: 產品頻率轉換器(乘積-頻率轉換器)
文件頁數: 11/16頁
文件大小: 155K
代理商: AD7750
AD7750
–11–
REV. 0
T able II. Maximum Output Frequencies
H(s) =
sRC
1 + sRC
R
C
R = 1M
V
C = 0.0707
m
F
Figure 16. HPF in Channel 1
C1
47nF
R2
33k
V
C2
33nF
VR2
200
V
R1
1M
V
PIN 7
VR1
100
V
R3
1.1k
V
860:1 ATTENUTATION
PIN 6
R4
1.1k
V
C3
33
m
F
Figure 17. Phase Lag Compensation on Channel 1 for
60 Hz Line Frequency
ADC 1
PGA
F
OUT
F1
F2
ADC 2
τ
V
1+
V
1–
V
2+
V
2–
X2
G1
ACDC
HPF
PHASE LEAD OF
2.58
8
C AT 50Hz
DIGITAL
MULTIPLIER
LPF
CLKIN
FS
S2
S1
TIME DELAY 143
m
s
(CLKIN = 3.5795MHz)
2.58
8
C AT 50Hz
DIGITAL-TO-FREQUENCY BLOCK
COUNTER/ACCUMULATOR
DTF
Figure 15. Equivalent AD7750 Signal Processing Chain
e
d
0
1
2
3
4
5
6
7
o
M
S
F
2
0
0
1
1
0
0
1
1
S
1
0
1
0
1
0
1
0
1
S
)
H
(
2
F
)
±
9
9
9
±
±
8
o
8
o
±
6
1
,
D
F
(
8
0
0
8
6
1
0
0
C
F
(
1
0
0
2
2
0
0
2
T
U
C
9
O
)
H
(
)
±
2
4
±
±
9
1
±
D
0
o
o
1
1
o
o
1
)
H
(
2
F
)
±
4
4
4
±
±
9
o
9
o
±
6
1
,
A
F
(
8
0
0
8
6
1
0
0
C
F
(
1
0
0
2
2
0
0
2
T
U
C
9
O
)
H
(
)
±
1
2
±
±
4
9
±
A
0
o
o
1
1
o
o
1
0
0
0
0
1
1
1
1
9
6
4
5
4
3
2
o
o
3
6
5
5
o
o
5
3
1
4
6
2
1
2
4
2
1
9
8
8
5
2
4
6
8
8
8
9
2
8
4
1
8
2
4
8
9
2
4
8
Digital-to-Frequency Converter (DT F)
After they have been filtered, the outputs of the two sigma-delta
modulators are fed into a digital multiplier. T he output of the
multiplier is then low-pass filtered to obtain the real power
information. T he output of the LPF enters a digital-to-frequency
converter whose output frequency is now proportional to the
real power. T he DT F offers a range of output frequencies to
suit most power measurement applications. T here is also a high
frequency output called F
OUT
, which can be used for calibra-
tion purposes. T he output frequencies are determined by the
logic inputs FS, S2 and S1. T his is explained in the section of
this data sheet called Determining the Output Frequencies of
the AD7750.
Figure 18 shows the waveforms of the various frequency out-
puts. T he outputs F1 and F2 are the low frequency outputs
that can be used to directly drive a stepper motor or electrome-
chanical pulse counter. T he F1 and F2 outputs provide two
alternating low going pulses. T he pulsewidth is set at 275 ms
and the time between the falling edges of F1 and F2 is ap-
proximately half the period of F1. If, however, the period of
F1 and F2 falls below 550 ms (1.81 Hz) the pulsewidth of F1
and F2 is set to half the period. For example in Mode 3,
where F1 and F2 vary around 6.8 Hz, the pulsewidth would vary
from 1/2.(6.8+1.45) seconds to 1/2.(6.8–1.45) seconds—see
T able II.
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參數描述
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