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參數資料
| 型號： | AD7801BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +2.7 V to +5.5 V, Parallel Input, Voltage Output 8-Bit DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 1.2 us SETTLING TIME, 8-BIT DAC, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數： | 10/16頁 |
| 文件大小： | 219K |
| 代理商： | AD7801BR |
AD7801
–10–
REV. 0
Figure 27 shows a typical setup for the AD7801 when using its
internal reference. T he internal reference is selected by tying the
REFIN pin to V
DD
. Internally in the reference section there is a
reference detect circuit that will select the internal V
DD
/2 based
on the voltage connected to the REFIN pin. If REFIN is within
a threshold voltage of a PMOS device (approximately 1 V) of
V
DD
the internal reference is selected. When the REFIN voltage
is more than 1 V below V
DD
, the externally applied voltage at
this pin is used as the reference for the DAC. T he internal
reference on the AD7801 is V
DD
/2, the output current to
voltage converter within the AD7801 provides a gain of two.
T hus the output range of the DAC is from 0 V to V
DD
, based on
T able I.
DATA BUS
CONTROL
INPUTS
AD7801
CS
WR
LDAC
V
OUT
V
OUT
D7-D0
CLR
PD
V
DD
REF IN
V
DD
= 3V TO 5V
V
DD
AGND DGND
10
m
F
0.1
m
F
Figure 27. Typical Configuration Selecting the Internal
Reference
Figure 28 shows a typical setup for the AD7801 when using an
external reference. T he reference range for the AD7801 is from
1 V to V
DD
/2 V. Higher values of reference can be incorporated
but will saturate the output at both the top and bottom end of
the transfer function. T here is a gain of two from input to output
on the AD7801. Suitable references for 5 V operation are the
AD780 and REF192. For 3 V operation a suitable external
reference would be the AD589 a 1.23 V bandgap reference.
DATA BUS
CONTROL
INPUTS
AD7801
CS
WR
LDAC
V
OUT
V
OUT
D7-D0
CLR
PD
V
DD
REF IN
V
DD
= 3V TO 5V
V
DD
AGND DGND
10
m
F
0.1
m
F
0.1
m
F
EXT REF
V
OUT
V
IN
GND
AD780/REF192 WITH V
DD
= 5V
OR
AD589 WITH V
DD
= 3V
Figure 28. Typical Configuration Using An External
Reference
MICROPROCE SSOR INT E RFACING
AD7801–ADSP-2101/ADSP-2103 Interface
Figure 29 shows an interface between the AD7801 and the ADSP-
2101/ADSP-2103. T he fast interface timing associated with the
AD7801 allows easy interface to the ADSP-2101/ADSP-2103.
LDAC
is permanently tied low in this circuit so the DAC
output is updated on the rising edge of the
WR
signal.
Data is loaded to the AD7801 input register using the following
ADSP-21xx instruction.
DM(DAC) = MR0
MR0 = ADSP-21xx MR0 Register.
DAC = Decoded DAC Address.
ADDR
DECODE
EN
ADDRESS BUS
AD7801*
CS
LDAC
WR
DB7
DB0
DATA BUS
*
ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
DMA14
DMA0
DMS
WR
DMD15
DMD0
ADSP-2101*/
ADSP-2103*
Figure 29. AD7801–ADSP-2101/ADSP-2103 Interface
AD7801–T MS320C20 Interface
Figure 30 shows an interface between the AD7801 and the
T MS320C20. Data is loaded to the AD7801 using the following
instruction:
OUT DAC, D
DAC = Decoded DAC Address.
D = Data Memory Address.
ADDR
DECODE
EN
ADDRESS BUS
AD7801*
CS
LDAC
WR
DB7
DB0
DATA BUS
*
ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
A15
A0
IS
STRB
D15
D0
TMS320C20
R/
W
Figure 30. AD7801–TMS320C20 Interface
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