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參數資料
| 型號： | AD7823YRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2.7 V to 5.5 V, 4.5 us, 8-Bit ADC in 8-Lead microSOIC/DIP |
| 中文描述： | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MICRO, SOIC-8 |
| 文件頁數： | 7/11頁 |
| 文件大小： | 155K |
| 代理商： | AD7823YRM |
AD7823
–7–
REV. B
When using the pseudo differential input scheme the signal on
V
IN–
must not vary by more than a 1/2 LSB during the conver-
sion process. If the signal on V
IN–
varies during conversion, the
conversion result will be incorrect. For single ended operation,
V
IN–
is always connected to AGND. Figure 9 shows the AD7823
pseudo differential input being used to make a unipolar dc current
measurement. A sense resistor is used to convert the current to a
voltage, and the voltage is applied to the differential input as
shown.
V
DD
R
SENSE
R
L
V
IN+
V
IN
–
AD7823
Figure 9. DC Current Measurement Scheme
DC Acquisition Time
The ADC starts a new acquisition phase at the end of a conver-
sion and ends on the falling edge of the
CONVST
signal. At the
end of a conversion there is a settling time associated with the
sampling circuit. This settling time lasts approximately 100 ns.
The analog signal on V
IN+
is also being acquired during this
settling time; therefore, the minimum acquisition time needed is
approximately 100 ns.
Figure 10 shows the equivalent charging circuit for the sampling
capacitor when the ADC is in its acquisition phase. R2 repre-
sents the source impedance of a buffer amplifier or resistive
network; R1 is an internal multiplexer resistance and C1 is the
sampling capacitor.
C1
3.5 F
R1
125
V
IN+
R2
Figure 10. Equivalent Sampling Circuit
During the acquisition phase, the sampling capacitor must be
charged to within a 1/2 LSB of its final value. The time it takes
to charge the sampling capacitor (t
CHARGE
) is given by the
following formula:
t
CHARGE
= 6.2
×
(
R
2 + 125
)
×
3.5
pF
For small values of source impedance, the settling time associ-
ated with the sampling circuit (100 ns) is, in effect, the acquisi-
tion time of the ADC. For example, with a source impedance
(R2) of 10
, the charge time for the sampling capacitor is
approximately 2 ns. The charge time becomes significant for
source impedances of 4.6 k
and greater.
AC Acquisition Time
In ac applications it is recommended to always buffer analog
input signals. The source impedance of the drive circuitry must
be kept as low as possible to minimize the acquisition time of
the ADC. Large values of source impedance will cause the THD
to degrade at high throughput rates. In addition, better perfor-
mance can generally be achieved by using an external 1 nF
capacitor on V
IN+
.
ADC TRANSFER FUNCTION
The output coding of the AD7823 is straight binary. The
designed code transitions occur at successive integer LSB values
(i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = V
REF
/256. The
ideal transfer characteristic for the AD7823 is shown in Figure
11 below.
000...010
000...001
000...000
A
0V
+V
REF
–
1LSB
ANALOG INPUT
111...111
111...110
111...000
011...111
1LSB
1LSB = V
REF
/256
Figure 11. Transfer Characteristic
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