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參數資料
| 型號： | AD7924 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP |
| 中文描述： | 4通道，1 MSPS的，8-/10-/12-Bit ADC的16與序列鉛TSSOP封裝 |
| 文件頁數： | 21/24頁 |
| 文件大小： | 411K |
| 代理商： | AD7924 |
AD7904/AD7914/AD7924
–21–
REV. 0
Figure 15 shows the maximum power versus throughput rate
when using the Auto Shutdown mode with 5 V and 3 V supplies.
THROUGHPUT – kSPS
10
0
100
200
300
P
1
0.1
0.01
50
150
250
350
V
DD
= 5V
V
DD
= 3V
Figure 15. AD7924 Power vs. Throughput Rate
SERIAL INTERFACE
Figures 16, 17, and 18 show the detailed timing diagrams for
serial interfacing to the AD7904, AD7914, and AD7924,
respectively. The serial clock provides the conversion clock and
also controls the transfer of information to and from the
AD7904/AD7914/AD7924 during each conversion.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
puts the track and hold into hold mode,
takes the bus out of three-state and the analog input is sampled
at this point. The conversion is also initiated at this point and
will require 16 SCLK cycles to complete. The track and hold
will go back into track on the fourteenth SCLK falling edge as
shown in Figures 16, 17, and 18 at Point B. On the sixteenth
SCLK falling edge, the DOUT line will go back into three-state.
If the rising
edge of
CS
occurs before 16 SCLKs have elapsed,
the conversion
will be terminated, the DOUT line will go back
into three-state, and the Control Register will not be updated;
otherwise DOUT returns to three-state on the sixteenth SCLK
falling edge as shown in Figures 16, 17, and 18.
CS
SCLK
DOUT
DIN
t
2
t
3
t
9
SEQ1
t
4
t
7
t
5
t
11
t
8
t
QUIET
t
6
t
CONVERT
1
2
3
4
5
6
11
12
13
14
15
16
THREE-
STATE
ZERO
ADD1
2 IDENTIFICATION
BITS
ADD0
DB7
DB6
DB0
ZERO
ZERO
4 TRAILING ZEROS
ZERO
ZERO
THREE-
STATE
t
10
ZERO
B
WRITE
DONTC
DONTC
ADD1
ADD0
CODING
DONTC
DONTC
DONTC
DONTC
Figure 16. AD7904 Serial Interface Timing Diagram
CS
SCLK
DOUT
DIN
t
2
t
3
t
9
SEQ1
t
4
t
7
t
5
t
11
t
8
t
6
t
CONVERT
1
2
3
4
5
6
11
12
13
14
15
16
THREE-
STATE
ZERO
ADD1
2 IDENTIFICATION
BITS
ADD0
DB9
DB8
DB2
DB1
DB0
ZERO
2 TRAILING ZEROS
ZERO
THREE-
STATE
t
10
ZERO
B
WRITE
DONTC
DONTC
ADD1
ADD0
CODING
DONTC
DONTC
DONTC
DONTC
t
QUIET
Figure 17. AD7914 Serial Interface Timing Diagram
CS
SCLK
DOUT
DIN
t
2
t
3
t
9
SEQ1
t
4
t
7
t
5
t
11
t
8
t
6
t
CONVERT
1
2
3
4
5
6
11
12
13
14
15
16
THREE-
STATE
ZERO
ADD1
2 IDENTIFICATION
BITS
ADD0
DB11
DB10
DB4
DB3
DB2
DB1
DB0
THREE-
STATE
t
10
ZERO
B
WRITE
DONTC
DONTC
ADD1
ADD0
CODING
DONTC
DONTC
DONTC
DONTC
t
QUIET
Figure 18. AD7924 Serial Interface Timing Diagram
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