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參數(shù)資料
型號: AD7943
廠商: Analog Devices, Inc.
英文描述: +3.3 V/+5 V Multiplying 12-Bit DACs(12位乘法D/A轉(zhuǎn)換器)
中文描述: 3.3伏/ 5伏乘以12位DAC(12位乘法的D / A轉(zhuǎn)換器)
文件頁數(shù): 5/16頁
文件大小: 340K
代理商: AD7943
AD7943/AD7945/AD7948
REV. B
–5–
(T
A
= T
MIN
to T
MAX
, unless otherwise noted)
Limit @
V
DD
= +3 V to +3.6 V
Limit @
V
DD
= +4.5 V to +5.5 V
Parameter
t
STB2
t
DS
t
DH
t
SRI
t
LD
t
CLR
t
ASB
Units
Description
60
15
35
55
55
55
0
40
10
25
35
35
35
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
STB Pulsewidth
Data Setup Time
Data Hold Time
SRI Data Pulsewidth
Load Pulsewidth
CLR Pulsewidth
Min Time Between Strobing Input Shift
Register and Loading DAC Register
STB Clocking Edge to SRO Data Valid Delay
t
SV3
60
35
ns max
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. tr and tf should not exceed 1
μ
s on any digital input.
2
STB mark/space ratio range is 60/40 to 40/60.
3
t
SV
is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Specifications subject to change without notice.
t
STB
STB1,
STB2,
STB4
STB3
t
DS
t
DH
t
SRI
SRI
DB11(N)
(MSB)
DB10(N)
DB0(N)
DB0(N–1)
DB10(N–1)
LD1
,
LD2
,
CLR
SRO
t
SV
t
LD,
t
CLR
t
ASB
Figure 1. AD7943 Timing Diagram
TO OUTPUT
PIN
C
L
50pF
1.6mA
I
OL
+2.1V
I
OH
200
m
A
Figure 2. Load Circuit for Digital Output Timing Specifications
AD7943 TIMING SPECIFICATIONS
1
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