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參數(shù)資料
型號: AD7993BRU-0
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 4-Channel, 12-/10-Bit ADCs with I2C Compatible Interface in 16-Lead TSSOP
中文描述: 4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16
封裝: MO-153-AB, TSSOP-16
文件頁數(shù): 27/27頁
文件大小: 277K
代理商: AD7993BRU-0
AD7994/AD7993
–27–
REV. PrF
PRELIMINARY TECHNICAL DATA
16-Lead TSSOP (RU-16)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16
9
8
1
0.201 (5.10)
0.193 (4.90)
0
0
0
0
PIN
1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
It is recommended that no I
2
C Bus activity occurs when a
conversion is taking place. However if this is not possible,
e.g. when operating in Mode 2 or Mode 3, then in order
to maintain the performance of the ADC, Bits D7 and D6
in the Cycle Timer Register are used to delay critical
sample intervals and bit trials from occurring while there
is activity on the I
2
C Bus. This will result in a quiet pe-
riod for each bit decision. In certain cases where there is
excessive activity on the interface lines this may have the
effect of increasing the overall Conversion time. However
if bit trial delays extend longer than 1 μs the conversion
will terminate.
When bits D7 and D6 are both 0, the bit trial and sample
interval delaying mechanism will be implemented. The
default setting of D7 and D6 is 0. To turn off both set D7
and D6 to 1.
D7
D6
D5
D4
D3
D2
D1
D0
Sample Bit Trial 0
Dealy
Delay
0
0
Cyc
Bit2
Cyc
Bit1
Cyc
Bit0
0*
0*
0*
0*
0*
0*
0*
0*
Cycle Timer Register
*Default settings at Power-up
相關(guān)PDF資料
PDF描述
AD7993 4-Channel, 12-/10-Bit ADCs with I2C Compatible Interface in 16-Lead TSSOP
AD7994 4-Channel, 12-/10-Bit ADCs with I2C Compatible Interface in 16-Lead TSSOP
AD7993BRU-1 4-Channel, 12-/10-Bit ADCs with I2C Compatible Interface in 16-Lead TSSOP
AD7997 8-Channel, 10- and 12-Bit ADCs with I2CCompatible
AD7997BRU-0 8-Channel, 10- and 12-Bit ADCs with I2CCompatible
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