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參數資料
| 型號： | AD803 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Clock Recovery and Data Retiming Phase-Locked Loop(時鐘恢復和重定時PLL) |
| 中文描述： | 時鐘恢復和數據重定時鎖相環（時鐘恢復和重定時鎖相環） |
| 文件頁數： | 3/4頁 |
| 文件大小： | 129K |
| 代理商： | AD803 |
AD803
–3–
REV. 0
ABSOLUTE MAXIMUM RATINGS*
Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.5 V
Input Voltage (Pin 19 to V
CC
) . . . . . . . . . . . . . . . . . +300 mV
Storage Temperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
Lead Temperature Range (Soldering 60 see) . . . . . . . . . 300
°
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may adversely affect device reliability.
TOP VIEW
ESU(Not to Scale)
1
2
19
5
6
7
16
15
14
4
18
17
8
13
9
12
10
11
AD803
NC = NO CONNECT
TSUBST
DATAIN
ESUBST
EV
EE
EV
CC
TV
CC
NC
AV
CC
CF1
CF2
TV
EE
DATAOUT
TV
EE
EV
EE
TV
CC
CLKOUT
EV
CC
AV
EE
ASUBST
TTL
DATA
OUT
TTL DATA IN (NRZ)
5V
0.1
0.1
5V
0.1
C
D
5V
TTL
CLOCK
OUT
0.1
0.1
5V
= ANALOG GROUND
= DIGITAL GROUND
20
3
Application/Test Circuit
t
RCS
CLKOUT
50%
DATAOUT
50%
Figure 1. Recovered Clock Skew (See Specifications)
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD803
NC = NO CONNECT
TV
EE
NC
TV
CC
DATAIN
TSUBST
DATAOUT
TV
CC
CLKOUT
EV
CC
EV
EE
ESUBST
TV
EE
ESUBST
EV
EE
EV
CC
AV
EE
ASUBST
CF2
CF1
AV
CC
NOTES:
PINS 6 & 16 ARE DIGITAL
SUBSTRATE AND SHOULD BE
CONNECTED TO PINS 7 & 15,
WHICH ARE DIGITAL V
EE.
PIN 10 IS ANALOG SUBSTRATE
AND SHOULD BE CONNECTED TO
PIN 9 WHICH IS ANALOG V
EE.
PIN FUNCTION DESCRIPTIONS
Mnemonic
Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TV
EE
DATAOUT
TV
CC
CLKOUT
TV
EE
ESUBST
EV
EE
EV
CC
AV
EE
ASUBST
CF2
CF1
AV
CC
EV
CC
EV
EE
ESUBST
NC
TV
CC
DATAIN
TSUBST
Digital Ground
Retimed Data Output
Digital V
CC
Recovered Clock Output
Digital Ground
Digital Substrate
Digital V
EE
Digital V
CC
Analog V
EE
Analog Substrate
Loop Damping Capacitor Input
Loop Damping Capacitor Input
Analog V
CC
Digital V
CC
Digital V
EE
Digital Substrate
No Connection
Digital V
CC
Data Input
Digital Substrate
ORDERING GUIDE AND THERMAL CHARACTERISTICS
Model
Description
Operating Temperature
u
JA
Package Option
AD803-20BR
20-Pin SOIC
–40
°
C to +85
°
C
75
°
C/W
R-20
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD803 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
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