
AD8116
–22–
REV. 0
Optimized for video applications, all signal inputs and outputs
are terminated with 75
resistors. Stripline techniques are
used to achieve a characteristic impedance on the signal input
and output lines also of 75
. Figure 34 shows a cross-section
of one of the input or output tracks along with the arrangement
of the PCB layers. It should be noted that unused regions of the
four layers are filled up with ground planes. As a result, the
input and output traces, in addition to having controlled
impedances, are well shielded.
w = 0.008"
(0.2mm)
a = 0.008"
(0.2mm)
b = 0.024"
(0.6mm)
h = 0.011325"
(0.288mm)
t = 0.00135" (0.0343mm)
TOP LAYER
SIGNAL LAYER
POWER LAYER
BOTTOM LAYER
Figure 34. Cross Section of Input and Output Traces
The board has 32 BNC type connectors: 16 inputs and 16
outputs. The connectors are arranged in two crescents around
the device. As can be seen from Figure 31, this results in all
sixteen input signal traces and all sixteen signal output traces
having the same length. This is useful in tests such as All-
Hostile Crosstalk where the phase relationship and delay
between signals needs to be maintained from input to output.
The four power supply pins AVCC, DVCC, AVEE and DVEE
should be connected to good quality, low noise,
±
5 V supplies.
Where the same
±
5 V power supplies are used for analog and
digital, separate cables should be run for the power supply to
the evaluation board’s analog and digital power supply pins.
As can be seen in Figure 35, there is extensive power supply
decoupling on the evaluation board. Figure 35 shows the
location of all the decoupling capacitors relative to the AD8116’s
pins. Four large 10
μ
F capacitors are located near the
evaluation board’s power supply connection terminals. These
decouple the AVCC, DVCC, AVEE and DVEE supplies.
Because it is required that the voltage difference between
DGND and AGND never exceed 0.7 V, these grounds are
connected by two antiparallel diodes. On the output side of the
device (Pin 65 to Pin 96), the sixteen output pins are inter-
leaved with the AVCC and AVEE power supply pins. Each of
these pins is locally decoupled with a 0.01
μ
F capacitor. These
pins are also decoupled in groups of four with 0.1
μ
F capacitors.
Due to space constraints the power supply Pins 34 (DVCC)
and 42 (DVEE) are neither connected nor decoupled. These
pins are, however, internally connected to DVCC and DVEE
(Pins 127 and 119).
As a general rule, each power supply pin (or group of adjacent
power supply pins) should be locally decoupled with a 0.01
μ
F
capacitor. If there is a space constraint, it is more important to
decouple analog power supply pins before digital power supply
pins. A 0.1
μ
F capacitor, located reasonably close to the pins,
can be used to decouple a number of power supply pins. Finally
a 10
μ
F capacitor should be used to decouple power supplies as
they come on to the board.