
AD8178
EQUIVALENT CIRCUITS
Rev. 0 | Page 19 of 40
0
1k
(VPOS – VNEG)
2
1k
OPn, ONn
Figure 8. Enabled Output (see also ESD Protection Map, Figure 19)
0
0.4pF
3.1k
20k
20k
3.4pF
3.4pF
OPn
VPOS
VNEG
20k
20k
VPOS
VNEG
ONn
Figure 9. Disabled Output (see also ESD Protection Map, Figure 19
)
0
1.3pF
1.3pF
0.3pF
IPn
INn
10k
2500
2500
5050
5050
Figure 10. Receiver Differential (see also ESD Protection Map, Figure 19)
0
1.3pF
1.3pF
0.3pF
IPn
INn
10k
2500
2500
Figure 11. Receiver Simplified Equivalent Circuit When Driving Differentially
0
1.6pF
IPn
INn
2.5k
Figure 12. Receiver Simplified Equivalent Circuit When Driving Single-Ended
0
0.1pF
VPOS
10k
0.1pF
10k
VNEG
VBLK,
VOCM_CMENCOFF
Figure 13. VBLK and VOCM_CMENCOFF Inputs
(see also ESD Protection Map, Figure 19)
0
0.3pF
VPOS
3.33k
0.3pF
3.33k
VNEG
VOCM_CMENCON
Figure 14. VOCM_CMENCON Input (see also ESD Protection Map, Figure 19
)
0
RST
VDD
DGND
1k
25k
Figure 15. RST Input (see also ESD Protection Map, Figure 19)
0
CLK, SER/PAR, WE,
UPDATE, SERIN
A[2:0], D[4:0],
CMENC
DGND
1k
Figure 16. Logic Input (see also ESD Protection Map, Figure 19)
DGND
1k
25k
CS
0
Figure 17. CS Input (see also ESD Protection Map, Figure 19)