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參數資料
| 型號： | AD8221-EVAL |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier |
| 中文描述： | 單電源，軌至軌，低成本儀表放大器 |
| 文件頁數： | 14/20頁 |
| 文件大小： | 1283K |
| 代理商： | AD8221-EVAL |
AD8221
GAIN SELECTION
Placing a resistor across the R
G
terminals will set the AD8221’s
gain, which may be calculated by referring to Table 3 or by
using the gain equation
Rev. A | Page 14 of 20
1
kΩ
4
G
49
=
R
G
Table 3. Gains Achieved Using 1% Resistors
1% Std Table Value of R
G
()
49.9 k
12.4 k
5.49 k
2.61 k
1.00 k
499
249
100
49.9
The AD8221 defaults to G = 1 when no gain resistor is used.
Gain accuracy is determined by the absolute tolerance of R
G
.
The TC of the external gain resistor will increase the gain drift
of the instrumentation amplifier. Gain error and gain drift are
kept to a minimum when the gain resistor is not used.
Calculated Gain
1.990
4.984
9.998
19.93
50.40
100.0
199.4
495.0
991.0
LAYOUT
Careful board layout maximizes system performance. Traces
from the gain setting resistor to the R
G
pins should be kept as
short as possible to minimize parasitic inductance. To ensure
the most accurate output, the trace from the REF pin should
either be connected to the AD8221’s local ground as shown in
Figure 47, or connected to a voltage that is referenced to the
AD8221’s local ground.
Common-Mode Rejection
One benefit of the AD8221’s high CMRR over frequency is that
it has greater immunity to disturbances such as line noise and
its associated harmonics than do typical in-amps. These,
typically, have CMRR fall-off at 200 Hz; common-mode filters
are often used to compensate for this shortcoming. The AD8221
is able to reject CMRR over a greater frequency range, reducing
the need for filtering.
A well implemented layout helps to maintain the AD8221’s high
CMRR over frequency. Input source impedance and capacitance
should be closely matched. In addition, source resistance and
capacitance should be placed as close to the inputs as
permissible.
Grounding
The AD8221’s output voltage is developed with respect to the
potential on the reference terminal. Care should be taken to tie
REF to the appropriate “local ground.”
In mixed-signal environments, low level analog signals need to
be isolated from the noisy digital environment. Many ADCs
have separate analog and digital ground pins. Although it is
convenient to tie both grounds to a single ground plane, the
current traveling through the ground wires and PC board may
cause hundreds of millivolts of error. Therefore, separate analog
and digital ground returns should be used to minimize the
current flow from sensitive points to the system ground. An
example layout is shown in Figure 44 and Figure 45.
0
Figure 44.Top Layer of the AD8221-EVAL
0
Figure 45.Bottom Layer of the AD8221-EVAL
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