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參數(shù)資料
| 型號： | AD8318-EVAL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1 MHz - 8 GHz, 60 dB Logarithmic Detector/Controller |
| 中文描述： | 1兆赫- 8千兆赫，60分貝對數(shù)檢測器/控制器 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大小： | 2127K |
| 代理商： | AD8318-EVAL |
AD8318
Table 4. Input Impedance for Select Frequency
Rev. 0 | Page 13 of 24
S11
Frequency
MHz
Real
Imaginary
Impedance
(Series)
100
0.918
0.041
927-j491
456
0.905
0.183
173-j430
900
0.834
0.350
61-j233
1900
0.605
0.595
28-j117
2200
0.524
0.616
28-j102
3600
0.070
0.601
26-j49
5300
0.369
0.305
20-j16
5800
0.326
0.286
22-j16
8000
0.390
0.062
22-j3
OUTPUT INTERFACE
The VOUT pin is driven by a PNP output stage. An internal 10
resistor is placed in series with the emitter follower output and
the VOUT pin. The rise time of the output is limited mainly by
the slew on CLPF. The fall time is an RC limited slew given by
the load capacitance and the pull-down resistance at VOUT.
There is an internal pull-down resistor of 350 . Any resistive
load at VOUT is placed in parallel with the internal pull-down
resistor and provides additional discharge current.
0
+
0.2V
–
150
200
10
VOUT
VPSO
CLPF
CMOP
Figure 25. Output Interface
SETPOINT INTERFACE
The V
SET
input drives the high impedance (250 k
) input of an
internal op amp. The V
SET
voltage appears across the internal
3.13 k
resistor to generate I
SET
. When a portion of V
OUT
is
applied to VSET, the feedback loop forces I
D
× log
10
(V
IN
/V
INTERCEPT
) = I
SET
. If V
SET
= V
OUT
/X, then I
SET
=
V
OUT
/(X × 3.13 k
). The result is
V
OUT
= (I
D
× 3.13 k × X) × log
10
(V
IN
/V
INTERCEPT
)
0
3.13k
I
SET
CMOP
VSET
Figure 26. VSET Interface
The slope is given by –I
D
× X × 3.13 k
= –500 mV × X. For
example, if a resistor divider to ground is used to generate a
V
SET
voltage of V
OUT
/2, then X = 2. The slope will be set to
–1 V/decade or –50 mV/dB.
TEMPERATURE COMPENSATION OF OUTPUT
VOLTAGE
The AD8318 functionality includes the capability to
externally trim the temperature drift. Attaching a ground-
referenced resistor to the T
ADJ
pin alters an internal current,
which works to minimize intercept drift vs. temperature. As
a result, the T
ADJ
resistor can be optimized for operation at
different frequencies.
0
2k
I
COMP
~0.4V
TADJ
2V
INTERNAL
V
Figure 27. TADJ Interface
A resistor, nominally 500
for optimal temperature
compensation at 2.2 GHz input frequency, is connected
between this pin and ground (see Figure 22). The value of
this resistor partially determines the magnitude of an analog
correction coefficient, which is employed to reduce
intercept drift.
Table 5 lists recommended resistors for other frequencies.
These resistors have been chosen to provide the best overall
temperature drift based on measurements of a diverse
population of devices.
The relationship between output temperature drift and
frequency is not linear and cannot be easily modeled. As a
result, experimentation is required to choose the correct
T
ADJ
resistor at frequencies not listed in Table 5.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8318-EVALZ | 功能描述:BOARD EVAL FOR AD8318 RoHS:是 類別:RF/IF 和 RFID >> RF 評估和開發(fā)套件，板 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關(guān)產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796 |
| AD8318SCPZ-EP-R2 | 制造商:Analog Devices 功能描述:1 MHZ TO 8 GHZ, 70 DB LOGARITHMIC DETECTOR / CONTROLLER - Tape and Reel |
| AD8318SCPZ-EP-RL7 | 制造商:Analog Devices 功能描述: |
| AD8318SCPZ-EP-WP | 制造商:Analog Devices 功能描述:1 MHZ TO 8 GHZ, 70 DB LOGARITHMIC DETECTOR / CONTROLLER - Waffle Pack |
| AD8318XCPZ | 制造商:Analog Devices 功能描述:100MHZ - 8GHZ, 70DB LOGARITHMIC DETECTOR/CONTROLLER - Bulk |
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