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參數資料
| 型號： | AD8326ARE-EVAL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ER 4C 4#0 PIN RECP |
| 中文描述： | 高輸出功率可編程有線電視線路驅動器 |
| 文件頁數： | 4/24頁 |
| 文件大小： | 475K |
| 代理商： | AD8326ARE-EVAL |
REV. 0
AD8326
LOGIC INPUTS (TTL/CMOS Compatible Logic)
–4–
Parameter
Min
T yp
Max
Unit
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (V
INH
= 5 V) CLK, SDATA,
DATEN
Logic “0” Current (V
INL
= 0 V) CLK, SDATA,
DATEN
Logic “1” Current (V
INH
= 5 V) TXEN
Logic “0” Current (V
INL
= 0 V) TXEN
Logic “1” Current (V
INH
= 5 V)
SLEEP
Logic “0” Current (V
INL
= 0 V)
SLEEP
2.1
0
0
–600
50
–250
50
–250
5.0
0.8
20
–100
190
–30
190
–30
V
V
nA
nA
μ
A
μ
A
μ
A
μ
A
Specifications subject to change without notice.
TIMNGREQUIREMENTS
Parameter
Min
T yp
Max
Unit
Clock Pulsewidth (t
WH
)
Clock Period (t
C
)
Setup Time SDATA vs. Clock (t
DS
)
Setup Time
DATEN
vs. Clock (t
ES
)
Hold Time SDATA vs. Clock (t
DH
)
Hold Time
DATEN
vs. Clock (t
EH
)
Input Rise and Fall Times, SDATA,
DATEN
, Clock (t
R
, t
F
)
16.0
32.0
5.0
15.0
5.0
3.0
ns
ns
ns
ns
ns
ns
ns
10
Specifications subject to change without notice.
t
ES
VALIMSB. . . .LSB
GAIN TRANSFER (G1)
t
DS
t
EH
8 CLOCK CYCLES
GAIN TRANSFER (G2)
t
OFF
t
GS
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
TXEN
CLK
SDATA
DATEN
t
ON
t
C
t
WH
VALID DATA WORD G2
Figure 2. Serial Interface Timing
VALID DATA BIT
MSB
MSB-1
MSB-2
t
DS
t
DH
SDATA
CLK
Figure 3. SDATA Timing
(Full Temperature Range, V
CC
= 12 V, t
R
= t
F
= 4 ns, f
CLK
= 8 MHz unless otherwse noted.)
(
DATEN
, CLK, SDATA, TXEN
SLEEP
, V
CC
= 12 V: Full Temperature Range)
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| AD8326ARE-REEL | 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single ±5.25V/12.6V 28-Pin TSSOP EP T/R 制造商:Rochester Electronics LLC 功能描述:TSSOP HIGH OUTPUT POWER CATV LINE DRIVER - Tape and Reel |
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| AD8326ARP-EVAL | 制造商:Analog Devices 功能描述:AD8326 PSOP EVALUATION BOARD 制造商:Analog Devices 功能描述:AD8326 PSOP EVALUATION BOARD - Bulk |
| AD8326ARP-REEL | 制造商:Analog Devices 功能描述: |
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