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參數(shù)資料
| 型號： | AD8326ARP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | High Output Power Programmable CATV Line Driver |
| 中文描述： | LINE DRIVER, PDSO28 |
| 封裝： | HEAT SINK, POWER, SOIC-28 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大小： | 475K |
| 代理商： | AD8326ARP |
REV. 0
AD8326
–6–
PIN FUNCT ION DE SCRIPT IONS
Pin No.
Mnemonic
Description
1
DATEN
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic
0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta-
neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch
(holds the previous gain state) and simultaneously enables the register for serial data load.
Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the
internal register with the MSB (Most Significant Bit) first and ignored.
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-
slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to
the slave. This requires the input serial data word to be valid at or before this clock transition.
Common External Ground Reference
Common Positive External Supply Voltage. A 0.1
μ
F capacitor must decouple each pin.
2
SDATA
3
CLK
4, 28
5, 9, 10, 19,
20, 23, 27
6
7
GND
V
CC
TXEN
SLEEP
Transmit Enable pin. Logic 1 powers up the part.
Low Power Sleep Mode. In the Sleep mode, the AD8326’s supply current is reduced to 4 mA. A
Logic 0 powers down the part (High Z
OUT
State) and a Logic 1 powers up the part.
No Connection to these pins.
Common Negative External Supply Voltage. A 0.1
μ
F capacitor must decouple each pin.
8, 12, 17
11, 13, 16, 18,
22, 24
14
15
21
25
NC
V
EE
OUT–
OUT+
BYP
V
IN+
Negative Output Signal
Positive Output Signal
Internal Bypass. This pin must be externally ac-coupled (0.1
μ
F capacitor).
Noninverting Input. DC-biased to approximately V
CC
/2. Should be ac-coupled with a
0.1
μ
F capacitor.
Inverting Input. DC-biased to approximately V
CC
/2. Should be ac-coupled with a 0.1
μ
F capacitor.
26
V
IN–
PIN CONFIGURAT ION
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD8326
DATEN
GND
SDATA
V
CC
V
IN
–
V
IN+
V
EE
V
CC
V
EE
BYP
CLK
GND
V
CC
TXEN
SLEEP
NC
V
CC
V
CC
V
EE
NC
V
CC
V
CC
V
EE
NC
V
EE
OUT
–
V
EE
OUT+
NC = NO CONNECT
相關(guān)PDF資料 |
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|---|---|
| AD8326 | High Output Power Programmable CATV Line Driver |
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| AD8327 | 5 V CATV Line Driver Coarse Step Output Power Control |
| AD8327-EVAL | 5 V CATV Line Driver Coarse Step Output Power Control |
| AD8327ARU | 5 V CATV Line Driver Coarse Step Output Power Control |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8326ARP-EVAL | 制造商:Analog Devices 功能描述:AD8326 PSOP EVALUATION BOARD 制造商:Analog Devices 功能描述:AD8326 PSOP EVALUATION BOARD - Bulk |
| AD8326ARP-REEL | 制造商:Analog Devices 功能描述: |
| AD8326ARPZ | 制造商:Analog Devices 功能描述:SP AMP LINE DRVR AMP SGL 5.25V/12.6V 28PSOP-II - Rail/Tube |
| AD8327 | 制造商:AD 制造商全稱:Analog Devices 功能描述:5 V CATV Line Driver Coarse Step Output Power Control |
| AD8327ARU | 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single 5.25V 20-Pin TSSOP Tube 制造商:Rochester Electronics LLC 功能描述:TSSOP COARSE STEP CATV LINE DRIVER - Bulk |
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