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參數資料
| 型號： | AD9761 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual 10-Bit TxDAC with 23 Interpolation Filters(內插濾波器的雙10位D/A轉換器) |
| 中文描述： | 雙10與23位插值濾波器TxDAC系列（內插濾波器的雙10位的D / A轉換器） |
| 文件頁數： | 16/24頁 |
| 文件大小： | 294K |
| 代理商： | AD9761 |
AD9761
–16–
REV. 0
DIFFE RE NT IAL USING AN OP AMP
An op amp can also be used to perform a differential to single-
ended conversion as shown in Figure 36. T he AD9761 is config-
ured with two equal load resistors, R
LOAD
, of 50
. T he differential
voltage developed across IOUT A and IOUT B is converted to a
single-ended signal via the differential op amp configuration. An
optional capacitor can be installed across IOUT A and IOUT B
forming a real pole in a low-pass filter. T he addition of this
capacitor also enhances the op amps distortion performance by
preventing the DACs high slewing output from overloading the
op amp’s input.
C
OPT
200
500
IOUTA
IOUTB
AD9761
R
LOAD
200
AD8042
500
R
LOAD
50
Figure 36. DC Differential Coupling Using an Op Amp
T he common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differen-
tial op amp circuit using the AD8042 is configured to provide
some additional signal gain. T he op amp must operate from a
dual supply since its output is approximately
±
1.0 V. A high
speed amplifier capable of preserving the differential performance
of the AD9761 while meeting other system level objectives (i.e.,
cost, power) should be selected. T he op amps differential gain, its
gain setting resistor values, and full-scale output swing capabili-
ties should all be considered when optimizing this circuit.
T he differential circuit shown in Figure 37 provides the neces-
sary level-shifting required in a single supply system. In this
case, AVDD, which is the positive analog supply for both the
AD9761 and the op amp is also used to level-shift the differen-
tial output of the AD9761 to midsupply (i.e., AVDD/2).
C
OPT
200
1k
IOUTA
IOUTB
AD9761
R
LOAD
200
AD8042
500
R
LOAD
50
1k
AVDD
Figure 37. Single-Supply DC Differential Coupled
Circuit
SINGLE -E NDE D UNBUFFE RE D VOLT AGE OUT PUT
Figure 38 shows the AD9761 configured to provide a unipolar
output range of approximately 0 V to +0.5 V since the nominal
full-scale current, I
OUT FS
, of 10 mA flows through an R
LOAD
of
50
. In the case of a doubly terminated low-pass filter, R
LOAD
represents the equivalent load resistance seen by IOUT A or
IOUT B. T he unused output (IOUT A or IOUT B) can be con-
nected to ACOM directly or via a matching R
LOAD
. Different
values of I
OUT FS
and R
LOAD
can be selected as long as the posi-
tive compliance range is adhered to.
50
IOUTA
IOUTB
AD9761
50
I
OUTFS
= 10mA
V
=
0V TO 0.5V
Figure 38. 0 V to +0.5 V Unbuffered Voltage Output
DIFFE RE NT IAL, DC COUPLE D OUT PUT
CONFIGURAT ION WIT H LE VE L SHIFT ING
Some applications may require the AD9761 differential outputs
to interface to a single supply quadrature upconverter. Although
most of these devices provide differential inputs, its common-
mode voltage range does not typically extend to ground. As a
result, the ground-referenced output signals shown in Figure 38
must be level shifted to within the specified common-mode
range of the single-supply quadrature upconverter. Figure 39
shows the addition of a resistor pull-up network which provides
the level shifting function. T he use of matched resistor networks
will maintain maximum gain matching and minimum offset
performance between the I and Q channels. Note, the resistor
pull-up network will introduce approximately 6 dB of signal
attenuation.
50
**
IOUTA
IOUTB
AD9761
50
**
500
*
500
*
500
*
500
*
AVDD
V
IN+
V
IN–
QUADRATURE
UPCONVERTER
*
OHMTEK TO MC-1603-5000D
**
OHMTEK TO MC-1603-1000D
Figure 39. Differential, DC Coupled Output Configuration
with Level-Shifting
POWE R AND GROUNDING CONSIDE RAT IONS
In systems seeking to simultaneously achieve high speed and
high performance, the implementation and construction of the
printed circuit board design is often as important as the circuit
design. Proper RF techniques must be used in device selection;
placement and routing; and supply bypassing and grounding.
T he evaluation board for the AD9761, which uses a four-layer
PC board, serves as a good example for the above mentioned
considerations. T he evaluation board provides an illustration of
the recommended printed circuit board ground, power and
signal plane layout.
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. T he AD9761 features
separate analog and digital supply and ground pins to optimize
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