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參數資料
| 型號： | AD9764* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit. 125 MSPS TxDAC D/A Converter |
| 中文描述： | 14位。 125 MSPS的TxDAC系列D / A轉換 |
| 文件頁數： | 2/22頁 |
| 文件大小： | 307K |
REV. B
–2–
AD9764–SPECIFICATIONS
DC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
RESOLUTION
DC ACCURACY
1
Integral Linearity Error (INL)
T
A
= +25
°
C
T
MIN
to T
MAX
Differential Nonlinearity (DNL)
T
A
= +25
°
C
T
MIN
to T
MAX
ANALOG OUTPUT
Offset Error
Gain Error
(Without Internal Reference)
Gain Error
(With Internal Reference)
Full-Scale Output Current
2
Output Compliance Range
Output Resistance
Output Capacitance
14
Bits
–4.5
–6.5
±
2.5
+4.5
+6.5
LSB
LSB
–2.5
–4.5
±
1.5
+2.5
+4.5
LSB
LSB
–0.025
–2
–7
2.0
–1.0
+0.025
+2
+7
20.0
1.25
% of FSR
% of FSR
% of FSR
mA
V
k
pF
±
1
±
1
100
5
REFERENCE OUTPUT
Reference Voltage
Reference Output Current
3
1.08
1.20
100
1.32
V
nA
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small Signal Bandwidth (w/o C
COMP1
)
4
0.1
1.25
V
M
MHz
1
1.4
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift
(Without Internal Reference)
Gain Drift
(With Internal Reference)
Reference Voltage Drift
0
±
50
±
100
±
50
ppm of FSR/
°
C
ppm of FSR/
°
C
ppm of FSR/
°
C
ppm/
°
C
POWER SUPPLY
Supply Voltages
AVDD
5
DVDD
Analog Supply Current (I
AVDD
)
Digital Supply Current (I
DVDD
)
6
Supply Current Sleep Mode (I
AVDD
)
Power Dissipation
6
(5 V, I
OUTFS
= 20 mA)
Power Dissipation
7
(5 V, I
OUTFS
= 20 mA)
Power Dissipation
7
(3 V, I
OUTFS
= 2 mA)
Power Supply Rejection Ratio
8
—AVDD
Power Supply Rejection Ratio
8
—DVDD
2.7
2.7
5.0
5.0
25
1.5
5.0
133
190
45
5.5
5.5
30
4
8.5
170
V
V
mA
mA
mA
mW
mW
mW
% of FSR/V
% of FSR/V
°
C
–0.4
–0.025
+0.4
+0.025
OPERATING RANGE
–40
+85
NOTES
1
Measured at I
, driving a virtual ground.
2
Nominal full-scale current, I
, is 32
×
the I
current.
3
Use an external buffer amplifier to drive any external load.
4
Reference bandwidth is a function of external cap at COMP1 pin and signal level.
5
For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.
6
Measured at f
= 25 MSPS and f
= 1.0 MHz.
7
Measured as unbuffered voltage output with I
OUTFS
= 20 mA and 50
R
LOAD
at I
OUTA
and I
OUTB
, f
CLOCK
= 100 MSPS and f
OUT
= 40 MHz.
8
±
5% Power supply variation.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, unless otherwise noted)
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