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參數資料
| 型號： | AD9767-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit, 125 MSPS Dual TxDAC+ D/A Converter |
| 中文描述： | 14位，125 MSPS的TxDAC系列雙D / A轉換 |
| 文件頁數： | 13/27頁 |
| 文件大小： | 469K |
| 代理商： | AD9767-EB |
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REV. B
AD9767
–13–
INPUT CLOCK AND DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9767 is rising edge triggered, and so
exhibits SNR sensitivity when the data transition is close to this
edge. In general, the goal when applying the AD9767 is to make
the data transition close to the falling clock edge. This becomes
more important as the sample rate increases. Figure 29 shows
the relationship of SNR to clock placement with different
sample rates. Note that at the lower sample rates, much more
tolerance is allowed in clock placement, while much more care
must be taken at higher rates.
TIME OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE
–
ns
S
–
0
–
4
–
2
0
2
3
–
3
–
1
4
1
10
20
30
40
50
60
70
80
Figure 29. SNR vs. Clock Placement @ f
OUT
= 20 MHz and
f
CLK
= 125 MSPS
SLEEP MODE OPERATION
The AD9767 has a power-down function that turns off the
output current and reduces the supply current to less than 8.5mA
over the specified supply range of 3.0 V to 5.5 V and tempera-
ture range. This mode can be activated by applying a Logic
Level “1” to the SLEEP pin. The SLEEP pin logic threshold is
equal to 0.5
×
AVDD. This digital input also contains an active
pull-down circuit that ensures the AD9767 remains enabled if
this input is left disconnected. The AD9767 takes less than
50 ns to power down and approximately 5
μ
s to power back up.
POWER DISSIPATION
The power dissipation, P
D
, of the AD9767 is dependent on
several factors that include: (1) The power supply voltages
(AVDD and DVDD), (2) the full-scale current output I
OUTFS
,
(3) the update rate f
CLOCK
, (4) and the reconstructed digital
input waveform. The power dissipation is directly proportional
to the analog supply current, I
AVDD
, and the digital supply cur-
rent, I
DVDD
. I
AVDD
is directly proportional to I
OUTFS
as shown
in Figure 30 and is insensitive to f
CLOCK
.
I
OUTFS
0
5
10
10
I
A
20
30
40
50
60
70
80
15
20
25
Figure 30. I
AVDD
vs. I
OUTFS
Conversely, I
DVDD
is dependent on both the digital input wave-
form, f
CLOCK
, and digital supply DVDD. Figures 31 and 32
show I
DVDD
as a function of full-scale sine wave output ratios
(f
OUT
/f
CLOCK
) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note how I
DVDD
is reduced by more
than a factor of 2 when DVDD is reduced from 5 V to 3 V.
RATIO
–
f
OUT
/f
CLK
0
0.1
0
I
D
–
5
10
15
20
25
30
35
0.2
0.3
0.4
0.5
125MSPS
100MSPS
65MSPS
25MSPS
5MSPS
Figure 31. I
DVDD
vs. Ratio @ DVDD = 5 V
RATIO
–
f
OUT
/f
CLK
0
0.1
0
I
D
–
2
4
6
8
10
12
14
0.2
0.3
0.4
0.5
16
18
125MSPS
100MSPS
65MSPS
25MSPS
5MSPS
Figure 32. I
DVDD
vs. Ratio @ DVDD = 3 V
相關PDF資料 |
PDF描述 |
|---|---|
| AD9767AST | 14-Bit, 125 MSPS Dual TxDAC+ D/A Converter |
| AD9768 | Ultrahigh Speed IC D/A Converter |
| AD9768SD | Ultrahigh Speed IC D/A Converter |
| AD9768SE | Ultrahigh Speed IC D/A Converter |
| AD9768JD | Ultrahigh Speed IC D/A Converter |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9767-EBZ | 功能描述:BOARD EVAL FOR AD9767 RoHS:是 類別:編程器，開發系統 >> 評估板 - 數模轉換器 (DAC) 系列:TxDAC+® 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數量:4 位數:12 采樣率（每秒）:- 數據接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9768 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultrahigh Speed IC D/A Converter |
| AD9768JD | 制造商:Rochester Electronics LLC 功能描述:AD9768 IC - Bulk |
| AD9768JQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9768SD | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultrahigh Speed IC D/A Converter |
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