
C8051F020/1/2/3
180
Rev. 1.4
Figure 17.21. P4: Port4 Data Register
Bits7-0:
P4.[7:0]: Port4 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See
Figure 17.20.Read - Returns states of I/O pins.
0: P4.n pin is logic low.
1: P4.n pin is logic high.
Note: P4.7 (/WR), P4.6 (/RD), and P4.5 (ALE) can be driven by the External Data Memory Interface.
R/W
Reset Value
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x84
Figure 17.22. P5: Port5 Data Register
Bits7-0:
P5.[7:0]: Port5 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See
Figure 17.20.Read - Returns states of I/O pins.
0: P5.n pin is logic low.
1: P5.n pin is logic high.
Note:
P5.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-multiplexed
on page 145 for more information about the External Memory Interface.
R/W
Reset Value
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x85