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參數資料
| 型號： | F50N06LE |
| 廠商： | Intersil Corporation |
| 英文描述： | 50A, 60V, 0.022 Ohm, Logic Level N-Channel Power MOSFETs |
| 中文描述： | 50A條，60V的，0.022歐姆，邏輯電平N溝道功率MOSFET |
| 文件頁數： | 5/8頁 |
| 文件大小： | 412K |
| 代理商： | F50N06LE |
5
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves
Unless Otherwise Specified
(Continued)
-80
-40
0
40
80
120
160
N
T
T
J
, JUNCTION TEMPERATURE (
o
C)
200
2.0
1.0
0.5
0
1.5
V
GS
= V
DS
, I
D
= 250
μ
A
1.2
1.0
0.9
0.8
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
N
B
200
1.1
I
D
= 250
μ
A
2500
2000
1000
0
0
5
10
15
20
25
C
C
RSS
1500
C
ISS
C
OSS
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
500
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
≈
C
DS
+ C
GD
60
45
30
15
0
20
(
)
)
---------------------
t, TIME (
μ
s)
80
(
)
)
---------------------
5.0
3.75
2.5
1.25
0
V
D
,
V
G
,
R
L
=1.2
I
G(REF)
= 1.2mA
V
GS
= 5V
V
DD
= BV
DSS
V
DD
= 0.75 BV
DSS
V
DD
= 0.50 BV
DSS
V
DD
= 0.25 BV
DSS
PLATEAU VOLTAGES IN
DESCENDING ORDER:
V
DD
= BV
DSS
V
DD
= BV
DSS
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
RFG50N06LE, RFP50N06LE, RF1S50N06LESM
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