
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
16/42
PCM interface
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60
°
C unless otherwise specified)
Symbol
Condition
fBCLK
CDL = 20 pF (during output)
dBCLK
CDL = 20 pF (during output)
fSYNC
CDL = 20 pF (during output)
dSYNC
1
BCLK = 2.048 MHz At output
tBS
BCLK to SYNC (during output)
tSB
SYNC to BCLK (during output)
tDS
tDH
tSDX
tXD1
tXD2
tXD3
Parameter
Min.
–0.1%
45
–0.1%
Typ.
2.048
50
8
Max.
+0.1%
55
+0.1%
Unit
MHz
%
kHz
Bit clock frequency
Bit clock duty ratio
Synchronous signal frequency
Synchronous signal duty ratio
CDL = 20 pF (during output)
45
50
55
%
100
100
50
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
100
100
100
100
ns
ns
ns
ns
ns
ns
ns
ns
Transmit/receive synchronous
timing
Input setup time
Input hold time
PCMI pin
Digital output delay time
Digital output hold time
PCMO pin
Pull-up resistance RDL = 500
CDL = 50 pF
0
1
MSB
LSB
tWS
tDS
tDH
BCLK
SYNC
PCMI
tBS
tSB
2
3
4
5
6
7
8
-
16
G.711
LSB
16-bit linear
Figure 2 PCM Interface Input Timing (Long Frame)
0
1
tWS
tDS
tDH
BCLK
SYNC
PCMI
tBS
tSB
2
3
4
5
6
7
8
9
-
MSB
LSB
G.711
17
LSB
16-bit linear
Figure 3 PCM Interface Input Timing (Short Frame)