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參數資料
| 型號： | IDTCSP59920-7SOI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 0.300 INCH, SOIC-24 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 96K |
| 代理商： | IDTCSP59920-7SOI |
1
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDTCSP59920
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
GND/sOE
Q0
Q1
REF
FS
PLL
FB
VDDQ /PE
Q2
Q3
Q4
Q5
Q6
Q7
FEBRUARY 2000
1999
Integrated Device Technology, Inc.
DSC-5813/-
c
IDTCSP59920
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
LOW SKEW
PLL CLOCK DRIVER
TURBOCLOCK JR.
DESCRIPTION:
The CSP59920 is a high fanout phase lock loop clock driver in-
tended for high performance computing and data-communications ap-
plications. The CSP59920 has CMOS outputs.
The CSP59920 maintains Cypress CY7B9920 compatibility while
providing two additional features: Synchronous Output Enable (GND/
sOE), and Positive/Negative Edge Synchronization (VDDQ/PE). When
the GND/
sOE pin is held low, all outputs are synchronously enabled
(CY7B9920 compatibility). However, if GND/
sOE is held high, all out-
puts except Q2 and Q3 are synchronously disabled.
Furthermore, when the VDDQ/PE is held high, all outputs are syn-
chronized with the positive edge of the REF clock input (CY7B9920
compatibility). When VDDQ/PE is held low, all outputs are synchronized
with the negative edge of REF.
The FB signal is compared with the input REF signal at the phase
detector in order to drive the VCO. Phase differences cause the VCO
of the PLL to adjust upwards or downwards accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
FEATURES:
Eight zero delay outputs
Selectable positive or negative edge synchronization
Synchronous output enable
Output frequency: 25MHz to 85MHz
CMOSoutputs
3 skew grades:
CSP59920-2: tSKEW0<250ps
CSP59920-5: tSKEW0<500ps
CSP59920-7: tSKEW0<750ps
3-level input for PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
46mA IOL high drive outputs
Low Jitter: <200ps peak-to-peak
Outputs drive 50
terminatedlines
Pin compatible with Cypress CY7B9920
Available in SOIC Package
FUNCTIONAL BLOCK DIAGRAM
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