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參數資料
| 型號： | IDTQS3ST253Q |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 編、解碼器及復用、解復用 |
| 英文描述： | DUAL 4 LINE TO 1 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PDSO20 |
| 封裝： | QSOP-20 |
| 文件頁數： | 6/10頁 |
| 文件大?。?/td> | 74K |
| 代理商： | IDTQS3ST253Q |
5
IDTQS3ST253
HIGH-SPEED CMOS SYNCHROSWITCH DUAL 4:1 MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Max.
Unit
ICCQ
Quiescent Power Supply Current
VCC = Max., VIN = GND or Vcc, f = 0
3
A
ICC
Power Supply Current per Control Input HIGH (2)
VCC = Max., VIN = 3.4V, f = 0
1.5
mA
ICCD
Dynamic Power Supply Current per MHz(3)
VCC = Max., A/B/C/D and Y pins open
0.25
mA/MHz
Control Inputs Toggling at 50% Duty Cycle
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Per TLL driven input (VIN = 3.4V, control inputs only). A/B/C/D and Y pins do not contribute to
Icc.
3. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The A/B/C/D and Y inputs generate
no significant AC or DC currents as they transition. This parameter is guaranteed but not production tested.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
TA = -40°C to +85°C, VCC = 5.0V ± 10%;
CLOAD = 50pF, RLOAD = 500
unless otherwise noted.
Symbol
Parameter
Min.(1)
Typ.
Max.
Unit
tPLH
DataPropagationDelays(1,2)
—
0.25
—
ns
tPHL
A/B/C/D to Y, Y to A/B/C/D
tSEC
Clock Enable to Clock Setup Time
3
—
ns
tHEC
Clock Enable to Clock Hold Time
0
—
ns
tCSO
Clock to Switch Turn-On Delay (3)
0.5
—
7
ns
tASO
Asynchronous Select to Switch Turn-On Delay (3)
0.5
—
7
ns
tW
Clock Pulse Width HIGH
3
—
ns
tSCS
SEL to Clock Setup Time
3
—
ns
tHCS
SEL to Clock Hold Time
0
—
ns
tPZL
Asynchronous Enable to Switch Turn-On Delay(3)
1.5
—
5.2
ns
tPZH
tPLZ
Asynchronous Enable to Switch Turn-Off Delay(1,3)
1.5
—
4.8
ns
tPHZ
NOTES:
1. This parameter is guaranteed but not tested.
2. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constraint for the switch
alone is of the order of 0.25ns for CL = 50pF. Since this time constant is much smaller than the rise and fall times of typical driving signals, it adds very little propagation
delay to the system. Propagation delay of the bus switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction
with the load on the driven side.
3. Minimums guaranteed but not tested.
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