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參數資料
| 型號： | LH6V4256 |
| 廠商： | Sharp Corporation |
| 英文描述： | CMOS 1M (256K x 4) Dynamic RAM |
| 中文描述： | 100萬的CMOS（256K × 4）動態隨機存儲器 |
| 文件頁數： | 1/18頁 |
| 文件大小： | 198K |
| 代理商： | LH6V4256 |
LH6V4256
CMOS 1M (256K
×
4) Dynamic RAM
FUNCTION
262,144 words
×
4 bit
Access time: 100 ns (MAX)
Cycle time: 190 ns (MIN)
Fast page mode cycle time: 60 ns (MIN)
Power supply: +3.3 V
±
0.3 V
Power consumption (MAX):
Operating: 126 mW
Standby: 0.54 mW
Built-in latch circuit for row-address,
column-address, and input data
OE = Don’t care in early write operation
RAS only refresh, hidden refresh, and
CAS before RAS refresh capability
On-chip refresh counter
512 refresh cycle/8 ms
Packages:
20-pin, 300-mil DIP
26-pin, 300-mil SOJ
28-pin, 8
×
13 mm
2
TSOP (Type I)
DESCRIPTION
The LH6V4256 is a 262,144 word
×
4-bit dynamic
RAM which allows fast page mode access. The
LH6V4256 is fabricated on SHARP’s advanced CMOS
double-level polysilicon gate technology. With its input
multiplexed and packaged in the standard 20-pin DIP,
26-pin SOJ, or 28-pin TSOP (I) packages, it is easy to
realize memory systems with low power dissipation and
large memory capacity. The LH6V4256 operates on a
single +3.3 V power supply and the built-in basing
voltage generator circuit.
PIN CONNECTIONS
6V4256-1
TOP VIEW
1
2
3
4
7
8
A
2
A
3
V
CC
NC
18
17
16
15
14
13
WE
RAS
5
6
A
1
A
0
12
11
CAS
A
8
A
7
A
6
A
5
A
4
9
10
20
19
I/O
4
V
SS
OE
20-PIN DIP
I/O
3
I/O
2
I/O
1
Figure 1. Pin Connections for DIP Package
2-14
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| LH6V4256D-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
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