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4.8 Port 6
4.8.2
Operation of port 6
This section describes the operations of port 5.
I
Operation of Port 6
H
Operation as an output port
If data is written into the PDR6 register, the data is retained on the output latch and then
output directly to the pins.
When using port 6 as an output port, it cannot be used for LCD controller/driver segment
output.
H
Operation during LCD controller/driver segment output
Set "1" to the bit of the PDR6 register corresponding to the LCD controller/driver segment
output pin to put the output transistor into high impedance (Prohibit UART output for P64 and
P65).
H
Operation as an input port
Pin values can be read by reading the PDR6 register (when the LCD controller/driver
segment output is not selected).
H
Operation during a reset
If CPU is reset, the value of the PDR6 register is initialized to "1". Thus, all output transistors
are turned "OFF" (input port) and the pins are put into high impedance.
H
Operation in stop mode and watch mode
If the pin state designate bit (STBC: SPL) of the standby control register is set to "1" when a
transition to the stop mode or watch mode occurs, the pins are put into high impedance. The
input is fixed to prevent leakage due to input opening.
Table 4.8-4 "Pin States of Port 6" lists the pin states of port 6.
Table 4.8-4 Pin States of Port 6
Pin name
Normal operation
Main sleep
Main stop (SPL=0)
Sub-sleep
Sub-stop (SPL=0)
Watch mode (SPL=0)
Main stop (SPL=1)
Sub-stop (SPL=1)
Watch mode (SPL=1)
During reset
P60 to P65
General-purpose I/O port/LCD
controller/driver segment output/
UART output
Hi-Z
(*1)
Hi-Z
SPL: Pin state designate bit of the standby control register (STBC: SPL)
Hi-Z: High impedance
*1: The previous state is retained during LCD controller/driver segment output.