
MC44724/5 Rev 0.21 03/25/97
No.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
4
I2C/SPI chip-address 40/41(hex)
1D/1E(hex)
[Block Diagram]
D
Y/G1
Y/G1
C/Cr/R1
C/Cr/R1
CVBS/Cb/B1
CVBS/Cb/B1
Y/G1Vdd
CVBS/Cb/B1Vdd
C/Cr/R1Vdd
E
F
H
DVIN [7 : 0]
0
0
0
0
CGMS,
WSS_gen
CC_gen
Sync_generator
copy
protection
bus
off_set
BG
Modulator
subcarrier
gen
0
D
0
D
0
TVIN
demux
Y
Cb
Cr
H,V
ChipA
DVdd
DVdd
DVss
DVss
MC44724/5
DAVdd
DAVss
Ibias1
B
Vref1
S
S
T
TEST
PAL/NTSC
Reset
clock
S
S
I2C / SPI
RGB matrix
0
0
0
D
Y/G2
Y/G2
C/Cr/R2
C/Cr/R2
CVBS/Cb/B2
CVBS/Cb/B2
D
D
Ibias2
B
Vref2
TP [8 : 1]
D
D
Y
C
C
O
bus
TP [0]