
Communications Processor (CP)
MOTOROLA
MC68302 USER’S MANUAL
4-143
E—Empty
0 = This bit is cleared by the CP to indicate that the data bits associated with this BD
are now available to the M68000 core.
1 = This bit is set by the M68000 core to indicate that the data bits associated with this
BD have been read.
NOTE
Additional data received will be discarded until the empty bit is
set by the M68000 core.
Bits 14–6—These bits are reserved and should be set to zero by the M68000 core.
C/I—Command/Indication Channel Data
Bits 1–0—The CP always writes these bits with zeros.
4.7.4.4 SMC2 Transmit Buffer Descriptor
In the IDL mode, this BD is identical to the SMC1 transmit BD. In the GCI mode, SMC2 is
used to control the C/I channel.
R—Ready
0 = This bit is cleared by the CP after transmission to indicate that the BD is now avail-
able to the M68000 core.
1 = This bit is set by the M68000 core to indicate that the data associated with this BD
is ready for transmission.
Bits 14–6—Reserved for future use; should be set to zero by the user.
C/I—Command/Indication Channel Data
Bits 1–0—These bits should be written with zeros by the M68000 core.
4.7.5 SMC Interrupt Requests
SMC1 and SMC2 send individual interrupt requests to the IMP interrupt controller when one
of the respective SMC receive buffers is full or when one of the SMC transmit buffers is emp-
ty. Each of the two interrupt requests from each SMC is enabled when its respective SMC
channel is enabled in the SPMODE register. Interrupt requests from SMC1 and SMC2 can
be masked in the interrupt mask register. See 3.2 Interrupt Controller for more details.
15
14
6
5
2
1
0
R
RESERVED
C/I
0
0