
CPU32+
MOTOROLA
MC68360 USER’S MANUAL
5-59
5.6 DEVELOPMENT SUPPORT
All M68000 family members have the following special features that facilitate applications
development.
Trace on Instruction Execution—All M68000 processors include an instruction-by-instruc-
tion tracing facility to aid in program development. The MC68020, MC68030, and CPU32+
can also trace those instructions that change program flow. In trace mode, an exception is
generated after each instruction is executed, allowing a debugger program to monitor exe-
cution of a program under test. See 5.5.2.10 Tracing for more information.
Breakpoint Instruction—An emulator can insert software breakpoints into target code to indi-
cate when a breakpoint occurs. On the MC68010, MC68020, MC68030, and CPU32+, this
function is provided via illegal instructions ($4848–$484F) that serve as breakpoint instruc-
tions. See 5.5.2.5 Software Breakpoints for more information.
Unimplemented Instruction Emulation—When an attempt is made to execute an illegal
line) utilize separate exception vectors to permit efficient emulation of unimplemented
instructions in software. See 5.5.2.8 Illegal or Unimplemented Instructions for more informa-
tion.
5.6.1 CPU32+ Integrated Development Support
In addition to standard MC68000 family capabilities, the CPU32+ has features to support
advanced integrated system development. These features include background debug
mode, deterministic opcode tracking, hardware breakpoints, and internal visibility in a sin-
gle-chip environment.
5.6.1.1 BACKGROUND DEBUG MODE (BDM) OVERVIEW.
Microprocessor
generally provide a debugger, implemented in software, for system analysis at the lowest
level. The BDM on the CPU32+ is unique because the debugger is implemented in CPU
microcode.
systems
BDM incorporates a full set of debug options—registers can be viewed and/or altered, mem-
ory can be read or written, and test features can be invoked.
A resident debugger simplifies implementation of an in-circuit emulator. In a common setup
(see Figure 5-18), emulator hardware replaces the target system processor. A complex,
expensive pod-and-cable interface provides a communication path between target system
and emulator.
Figure 5-18. In-Circuit Emulator Configuration
IN-CIRCUIT
EMULATOR
TARGET
MCU
TARGET
SYSTEM