
Timer Interface (TIM)
Data Sheet
MC68HC08AS32A — Rev. 1
242
Timer Interface (TIM)
MOTOROLA
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0020
Timer Status and Control
Register (TSC)
See page 253.
Read:
TOF
TOIE
TSTOP
0
0
PS2
PS1
PS0
Write:
0
TRST
Reset:
0
0
1
0
0
0
0
0
$0022
Timer Counter Register High
(TCNTH)
See page 254.
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
0
0
0
0
0
0
0
0
$0023
Timer Counter Register Low
(TCNTL)
See page 254.
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
0
0
0
0
0
0
0
0
$0024
Timer Modulo Register High
(TMODH)
See page 255.
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
1
1
1
1
1
1
1
1
$0025
Timer Modulo Register Low
(TMODL)
See page 255.
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
1
1
1
1
1
1
1
1
$0026
Timer Channel 0 Status and
Control Register (TSC0)
See page 256.
Read:
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Write:
0
Reset:
0
0
0
0
0
0
0
0
$0027
Timer Channel 0 Register High
(TCH0H)
See page 260.
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Indeterminate after reset
$0028
Timer Channel 0 Register Low
(TCH0L)
See page 260.
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Indeterminate after reset
$0029
Timer Channel 1 Status and
Control Register (TSC1)
See page 256.
Read:
CH1F
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
Write:
0
Reset:
0
0
0
0
0
0
0
0
$002A
Timer Channel 1 Register High
(TCH1H)
See page 260.
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Indeterminate after reset
$002B
Timer Channel 1 Register Low
(TCH1L)
See page 260.
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Indeterminate after reset
$002C
Timer Channel 2 Status and
Control Register (TSC2)
See page 256.
Read:
CH2F
CH2IE
MS2B
MS2A
ELS2B
ELS2A
TOV2
CH2MAX
Write:
0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-3. TIM I/O Register Summary
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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