
Memory Map
I/O section
MC68HC08AZ32
MOTOROLA
Memory Map
29
Addr.
$0000 Port A Data Register (PTA)R:
Name
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
W:
R:
W:
$0001
Port B Data Register
(PTB)
PTB7
PTB6
PTB25
PTB4
PTB3
PTB2
PTB1
PTB0
$0002
Port C Data RegisterR:
0
0
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
W:
R:
W:
R:DDRA7 DDRA6 DDRA5
W:
R:DDRB7 DDRB6 DDRB5
W:
R: MCLKE
N
W:
R:DDRD7 DDRD6 DDRD5
W:
R:
PTE7
PTE6
W:
0
PTF6
W:
R:
0
W:
R:
0
W:
R:DDRE7 DDRE6 DDRE5
W:
R:
0
DDRF6
W:
R:
0
W:
R:
0
W:
R:
SPRIE
DMAS
W:
R: SPRF
W:
$0003
Port D Data Register
(PTD)
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
$0004
Data Direction Register A
(DDRA)
DDRA4
DDRA3
DDRA2 DDRA1
DDRA0
$0005
Data Direction RegisterB
(DDRB)
DDRB4
DDRB3
DDRB2 DDRB1
DDRB0
$0006
Data Direction Register C
(DDRC)
0
DDRC5
DDRC4
DDRC3 DDRC2 DDRC1 DDRC0
$0007
Data Direction Register D
(DDRD)
DDRD4
DDRD3 DDRD2 DDRD1 DDRD0
$0008
Port E Data Register
(PTE)
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
$0009 Port F Data Register (PTF)R:
PTF5
PTF4
PTF3
PTF2
PTF1
PTF0
$000A
Port G Data Register
(PTG)
0
0
0
0
PTG2
PTG1
PTG0
$000B
Port H Data Register
(PTH)
0
0
0
0
0
PTH1
PTH0
$000C
Data Direction Register E
(DDRE)
DDRE4
DDRE3
DDRE2 DDRE1
DDRE0
$000D
Data Direction Register F
(DDRF)
DDRF5
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
$000E
Data Direction Register G
(DDRG)
0
0
0
0
DDRG2 DDRG1 DDRG0
$000F
Data Direction Register
(DDRH)
0
0
0
0
0
DDRH1 DDRH0
$0010
SPI Control Register
(SPCR)
SP-
MSTR
OVRF
CPOL
CPHA
SPWOM
SPE
SPTIE
$0011
SPI Status and Control
Register (SPSCR)
0
MODF
SPTE
0
SPR1
SPR0
$0012 SPI Data Register (SPDR)R:
Bit 7
6
5
4
3
2
1
Bit 0
W:
R:LOOPS ENSCI
W:
R:
SCTIE
W:
$0013
SCI Control Register 1
(SCC1)
TXINV
M
WAKE
ILTY
PEN
PTY
$0014
SCI Control Register 2
(SCC2)
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
= Unimplemented
R
= Reserved
Figure 2. Control, status, and data registers (Sheet 1 of 5)
5-mem