
Operating Modes and On-Chip Memory
EEPROM
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Operating Modes and On-Chip Memory
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59
ODD — Program Odd Rows in Half of EEPROM (Test) Bit
EVEN — Program Even Rows in Half of EEPROM (Test) Bit
ELAT — EPROM/OTPROM Latch Control Bit
For the MC68HC711E9, EPGM enables the high voltage necessary for both
EPROM/OTPROM and EEPROM programming.
For MC68HC711E9, ELAT and EELAT are mutually exclusive and cannot both
equal 1.
0 = EPROM address and data bus configured for normal reads
1 = EPROM address and data bus configured for programming
BYTE — Byte/Other EEPROM Erase Mode Bit
This bit overrides the ROW bit.
0 = Row or bulk erase
1 = Erase only one byte
ROW — Row/All EEPROM Erase Mode Bit
If BYTE is 1, ROW has no meaning.
0 = Bulk erase
1 = Row erase
ERASE — Erase Mode Select Bit
0 = Normal read or program mode
1 = Erase mode
EELAT — EEPROM Latch Control Bit
0 = EEPROM address and data bus configured for normal reads and cannot
be programmed
1 = EEPROM address and data bus configured for programming or erasing
and cannot be read
Address: $103B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ODD
EVEN
ELAT
(1)
BYTE
ROW
ERASE
EELAT
EPGM
Write:
Reset:
0
0
0
0
0
0
0
0
1. MC68HC711E9 only
Figure 2-17. EPROM and EEPROM Programming
Control Register (PPROG)
Table 2-8. EEPROM Erase
BYTE
0
0
1
1
ROW
0
1
0
1
Action
Bulk erase (entire array)
Row erase (16 bytes)
Byte erase
Byte erase
F
Freescale Semiconductor, Inc.
n
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