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參數資料
型號: MC74HC4020AN
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: 14-Stage Binary Ripple Counter
中文描述: HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDIP16
封裝: PLASTIC, DIP-16
文件頁數: 4/8頁
文件大小: 194K
代理商: MC74HC4020AN
MC74HC4020A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
3–4
TIMING REQUIREMENTS
(Input tr = tf = 6 ns)
Symbol
Parameter
V
Guaranteed Limit
Unit
VCC
–55 to 25
°
C
85
°
C
125
°
C
trec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
3.0
4.5
6.0
30
20
5
4
40
25
8
6
50
30
12
9
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
70
40
15
13
80
19
16
90
50
24
20
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
70
40
15
13
80
45
19
16
90
50
24
20
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
INPUTS
Clock (Pin 10)
Negative–edge triggering clock input. A high–to–low tran-
sition on this input advances the state of the counter.
Reset (Pin 11)
Active–high reset. A high level applied to this input asynch-
ronously resets the counter to its zero state, thus forcing all Q
outputs low.
OUTPUTS
Q1, Q4—Q14 (Pins 9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3)
Active–high outputs. Each Qn output divides the Clock
input frequency by 2N.
SWITCHING WAVEFORMS
tf
Clock
Q1
VCC
GND
90%
50%
10%
tr
tw
90%
50%
10%
tPHL
1/fMAX
tPLH
tTLH
tTHL
Clock
VCC
GND
tw
trec
50%
Figure 1.
Figure 2.
Reset
VCC
GND
50%
Any Q
50%
tPHL
相關PDF資料
PDF描述
MC74HC4024D 7-Stage Binary Ripple Counter
MC74HC4024N 7-Stage Binary Ripple Counter
MC74HC4049 Hex Buffers/Logic-Level Down Converters
MC74HC4049D Hex Buffers/Logic-Level Down Converters
MC74HC4050 Hex Buffers/Logic-Level Down Converters
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