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參數資料
| 型號： | NS32491 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Serial Network Interface |
| 中文描述： | 串行網絡接口 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 175K |
| 代理商： | NS32491 |
TL/F/6758
D
July 1986
DP8391/NS32491 Serial Network Interface
General Description
The DP8391 Serial Network Interface (SNI) provides the
Manchester data encoding and decoding functions for
IEEE 802.3 Ethernet/Cheapernet type local area networks.
The SNI interfaces the DP8390 Network Interface Controller
(NIC) to the Ethernet transceiver cable. When transmitting,
the SNI converts non-return-to-zero (NRZ) data from the
controller and clock pulses into Manchester encoding and
sends the converted data differentially to the transceiver.
The opposite process occurs on the receive path, where a
digital phase-locked loop decodes 10 Mbit/s signals with as
much as
g
20 ns of jitter.
The DP8391 SNI is a functionally complete Manchester en-
coder/decoder including ECL like balanced driver and re-
ceivers, on board crystal oscillator, collision signal transla-
tor, and a diagnostic loopback circuit.
The SNI is part of a three chip set that implements the com-
plete IEEE compatible network node electronics as shown
below. The other two chips are the DP8392 Coax Transceiv-
er Interface (CTI) and the DP8390 Network Interface Con-
troller (NIC).
Incorporated into the CTI are the transceiver, collision and
jabber functions. The Media Access Protocol and the buffer
management tasks are performed by the NIC. There is an
isolation requirement on signal and power lines between the
CTI and the SNI. This is usually accomplished by using a set
of miniature pulse transformers that come in a 16-pin plastic
DIP for signal lines. Power isolation, however, is done by
using a DC to DC converter.
Features
Y
Compatible with Ethernet II, IEEE 802.3 10base5 and
10base2 (Cheapernet)
Y
10 Mb/s Manchester encoding/decoding with receive
clock recovery
Y
Patented digital phase locked loop (DPLL) decoder re-
quires no precision external components
Y
Decodes Manchester data with up to
g
20 ns of jitter
Y
Loopback capability for diagnostics
Y
Externally selectable half or full step modes of opera-
tion at transmit output
Y
Squelch circuits at the receive and collision inputs re-
ject noise
Y
High voltage protection at transceiver interface (16V)
Y
TTL/MOS compatible controller interface
Y
Connects directly to the transceiver (AUI) cable
Table of Contents
1.0 System Diagram
2.0 Block Diagram
3.0 Functional Description
3.1
Oscillator
3.2
Encoder
3.3
Decoder
3.4
Collision Translator
3.5
Loopback
4.0 Connection Digram
5.0 Pin Description
6.0 Absolute Maximum Ratings
7.0 Electrical Characteristics
8.0 Switching Characteristics
9.0 Timing and Load Diagrams
10.0 Physical Dimensions
1.0 System Diagram
IEEE 802.3 Compatible Ethernet/Cheapernet Local Area Network Chip Set
TL/F/6758–1
C
1995 National Semiconductor Corporation
RRD-B30M115/Printed in U. S. A.
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相關代理商/技術參數 |
參數描述 |
|---|---|
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| NS32492B | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Coaxial Transceiver Interface |
| NS32532-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NS32532-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NS32532-30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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