
63
6.4
Electrical Characteristics Over Recommended Operating Free-Air Temperature
Range, TA = 0°C to 70°C (unless otherwise noted)
NOTE: In order to reach stated performance levels, the device’s PowerPad feature should be
thermally and electrically connected to the pcb ground plane, as described in Section 6.1
Designing With PowerPad.
6.4.1
Power Supply (3.3 V All Supplies)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog supply (=AVDD_CH1+AVDD_CH2_3+AVDD_PLL+AVDD_REF)
ADC_INTREF
325
385
mA
Analog supply (=AVDD_CH1+AVDD_CH2_3+AVDD_PLL+AVDD_REF)
ADC_INTREF
325
385
mA
Digital supply (=DVDD+DVDD_PLL)
ADC_INTREF
119
140
mA
Digital supply (=DVDD+DVDD_PLL)
ADC_INTREF
119
140
mA
Total power dissipation normal operation
ADC_INTREF
1.47
1.73
W
Total power dissipation normal operation
ADC_INTREF
1.47
1.73
W
Total power dissipation, power down all modes
ADC_PWDN
385
mW
Total power dissipation, power down all modes
ADC_PWDN
385
mW
6.4.2
Digital Logic Inputs (HS, VS, SCL, SDA, I2CA, XTL1_MCLK, EXT_ADCCLK, OE, RESET,
EXT_CLP)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH
High-level input current
10
A
IIL
Low-level input current
DVDD = 3.6 V,
Digital inputs and CLK at 0 V for IIL;
10
A
IIL(CLK)
Low-level input current, CLK (see Note 6)
Digital inputs and CLK at 0 V for IIL;
Digital inputs and CLK at 3.6 V for IIH
14
17
A
IIH(CLK) High-level input current , CLK (see Note 6)
Digital inputs and CLK at 3.6 V for IIH
14
17
A
CI
Input capacitance
5
pF
NOTE 6: Applies when XTL1_MCLK is driven by the clock signal directly.
6.4.3
Logic Outputs (SDA, CHn_OUTA[7..0], CHn_OUTB[7..0], DTOCLK3, ADCCLK2,
DATACLK1, DHS, LOCK)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
DVDD = 3 V at IOH = 50 A,
Digital output forced high
2.9
V
VOL
Low-level output voltage
DVDD = 3.6 V at IOL = 50 A,
Digital output forced low
0.15
V
CO
Output capacitance
5
pF
IOZ(H)/IOZ(L)
High-impedance-state output current
DVDD = 3.6 V
Worst case for VO = 3.6 V and VO = 0 V
10
A
Tested for CHn-A[7..0] and CHn_B[7..0] only