
v
7.4
Power Requirements
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7.4.1
Power for 700 mV DAC Output Compliance + 350 mV Bias
at AVDD = 3.3V, DVDD = 1.8V, VDD_IO = 3.3 V,
VDD_DLL = 3.3 V, 1-MHz Tone on All Channels
. . . . . . . .
7.4.2
Power for 700 mV DAC Output Compliance + 350 mV Bias
at AVDD = 3.3V, DVDD = 1.8 V, VDD_IO = 1.8V,
VDD_DLL = 3.3V, 1-MHz Tone on All Channels
. . . . . . . . .
7.4.3
Power for 1.25V Output Compliance Without Bias at
AVDD = 3.3 V, DVDD = 1.8 V, VDD_IO = 3.3 V,
VDD_DLL = 3.3 V, 1-MHz Tone on All Channels
. . . . . . . .
7.4.4
Power for 1.25V Without Bias at AVDD = 3.3 V,
DVDD = 1.8 V, VDD_IO = 1.8 V, VDD_DLL = 3.3 V,
1-MHz Tone on All Channels
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7.5
Nonlinearity
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7.5.1
Differential Nonlinearity (DNL) and Integral
Nonlinearity (INL) for 700 mV Without Bias
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7.5.2
Differential Nonlinearity (DNL) and Integral
Nonlinearity (INL) for 700 mV + 350 mV Bias
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7.5.3
Differential Nonlinearity (DNL) and Integral
Nonlinearity (INL) for 1.25 V Without Bias
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7.6
Analog Output Bandwidth (sinx/x corrected) at fS = 205 MSPS
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7.7
Output Compliance vs Full-Scale Adjustment Resistor Value
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7.8
Vertical Sync of the HDTV 1080I Format Preset in First and Second
Field, and Horizontal Line Waveform Detail
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8
Mechanical Information
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