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參數資料
型號: TLC320AD55CDWR
廠商: TEXAS INSTRUMENTS INC
元件分類: 模擬信號調理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO28
封裝: PLASTIC, SOP-28
文件頁數: 30/41頁
文件大小: 203K
代理商: TLC320AD55CDWR
A–2
Table A– 3. Control 2 Register
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
X
Reserved
X
Decimator FIR overflow flag (valid only during read cycle)
X
FLAG 1 output value
X
FLAG 0 output value
1
Phone mode enabled
0
Phone mode disabled
0
Normal operation with decimator FIR filter
1
Bypass decimator FIR filter
0
Normal operation with interpolator filter
1
Bypass interpolator FIR filter
Default register value: 00000000
Writing zeros to the reserved bits is suggested.
Table A– 4. Fk Divide Register
D7
D6
D5
D4
D3
D2
D1
D0
DIVIDE VALUE
1
255
1
000
0000
128
0
010
0000
32
0
000
0001
1
0
256
Default register value: 00001000
The oversampling clock (FCLK) is set as MCLK/(Fk
× 4). MCLK/(Fk × 256) is the sample frequency
(conversion rate) for the converter. When Fk is programmed to zero, its value is interpreted as 256.
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