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參數資料
| 型號： | W25P022AF-7 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | SRAM |
| 英文描述： | 64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| 中文描述： | 64K X 32 STANDARD SRAM, 7 ns, PQFP100 |
| 封裝： | MO-108, QFP-100 |
| 文件頁數： | 9/17頁 |
| 文件大小： | 310K |
| 代理商： | W25P022AF-7 |
W25P022A
Publication Release Date: September 1996
- 9 -
Revision A1
AC Timing Characteristics, continued
PARAMETER
SYM.
W25P022A-6
W25P022A-7
UNIT
NOTES
MIN.
MAX.
MIN.
MAX.
Clock Cycle Time
T
CYC
13.3
-
15
-
nS
Clock High Pulsh Width
T
KH
5
-
6
-
nS
Clock Low Pulse Width
T
KL
5
-
6
-
nS
Clock to Output Valid
T
KQ
-
6
-
7
nS
Clock to Output High-Z
T
KHZ
2
13.3
2
15
nS
1
Clock to Output Low-Z
T
KLZ
0
-
0
-
nS
1
Clock to Output Invalid
T
KX
2
-
2
-
nS
1
Output Enable to Output Valid
T
OE
-
6
-
7
nS
Output Enable to Output High-Z
T
OHZ
-
6
-
7
nS
1
Output Enable to Output Low-Z
T
OLZ
0
-
0
-
nS
1
Output Enable to Output Invalid
T
OX
0
-
0
-
nS
ZZ Standby Time
T
ZZS
-
100
-
100
nS
2
ZZ Recover Time
T
ZZR
100
-
100
-
nS
3
Notes:
1. These parameters are sampled but not 100% tested
2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active.
3. ADSC and ADSP should not be accessed for at least 100 nS after chip leaves ZZ mode.
4. Configuration signals LBO and FT are static and should not be changed during operation.
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