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參數資料
型號: W28V400BT85C
廠商: WINBOND ELECTRONICS CORP
元件分類: PROM
英文描述: 4M(512K x 8/256K x 16) SMARTVOLTAGE FLASH MEMORY
中文描述: 256K X 16 FLASH 2.7V PROM, 120 ns, PDSO48
封裝: 12 X 20 MM, TSOP-48
文件頁數: 28/48頁
文件大小: 1822K
代理商: W28V400BT85C
W28V400B/T
- 28 -
DC Characteristics (Continued)
V
DD
= 2.7V - 3.6V
V
DD
= 5V ±0.5V
PARAMETER
SYM.
TEST CONDITIONS
Min.
Max.
Min.
Max.
UNIT
Input Low Voltage (Note 7)
V
IL
-0.5
0.8
-0.5
0.8
V
Input High Voltage (Note 7)
V
IH
2.0
V
DD
+0.5
2.0
V
DD
+0.5
V
Output Low Voltage (Note 3, 7)
V
OL
V
DD
= V
DD
Min.
I
OL
= 5.8 mA (5V
±
0.5V)
I
OL
= 2.0 mA (3.3V
±
0.3V)
I
OL
= 2.0 mA (2.7V
3.6V)
0.4
0.45
V
Output High Voltage
(TTL) (Note 3, 7)
V
OH1
V
DD
= V
DD
Min.
I
OH
= -2.5 mA (5V
±
0.5V)
I
OH
= -2.0 mA (3.3V
±
0.3V)
I
OH
= -1.5 mA (2.7V
3.6V)
2.4
2.4
V
0.85 V
DD
0.85 V
DD
V
Output High Voltage
(CMOS) (Note 3, 7)
V
OH2
V
DD
= V
DD
Min.
I
OH
= -2.0 mA
V
DD
-0.4
V
DD
-0.4
V
V
PP
Lockout during Normal Operations
(Note 4, 7)
V
PPLK
V
DD
= V
DD
Min.
I
OH
= -100
μ
A
1.5
1.5
V
V
PP
during Block Erase or Word/Byte
Write Operations
V
PPH1
2.7
3.6
-
-
V
V
PP
during Block Erase or Word/Byte
Write Operations
V
PPH2
4.5
5.5
4.5
5.5
V
V
PP
during Block Erase or Word/Byte
Write Operations
V
PPH3
11.4
12.6
11.4
12.6
V
V
DD
Lockout Voltage
V
LKO
2.0
2.0
V
#RESET Unlock Voltage (Note 8, 9)
V
HH
Unavailable #WP
11.4
12.6
11.4
12.6
V
Notes:
1. All currents are in RMS unless otherwise noted. Typical values at nominal V
DD
voltage and T
A
= +25
°
C.
2. I
CCWS
and I
CCES
are specified with the device de-selected. If read or word/byte written while in erase suspend mode, the
device’s current draw is the sum of I
CCWS
or I
CCES
and I
CCR
or I
CCW
, respectively.
3. Includes RY/#BY.
4. Block erases and word/byte writes are inhibited when V
V
PPLK
, and not guaranteed in the range between V
(max.) and
V
PPH1
(min.), between V
PPH1
(max.) and V
PPH2
(min.), between V
PPH2
(max.) and V
PPH3
(min.), and above V
PPH3
(max.).
5. Automatic Power Savings (APS) reduces typical I
CCR
to 1mA at 5V V
DD
and 3 mA at 2.7V and 3.3V V
DD
in static operation.
6. CMOS inputs are either V
DD
±
0.2V or V
SS
±
0.2V. TTL inputs are either V
IL
or V
IH
.
7. Sampled, not 100% tested.
8. Boot block erases and word/byte writes are inhibited when the corresponding #RESET = V
IH
and #WP = V
IL
. Block erase and
word/byte write operations are not guaranteed with V
IH
< #RESET < V
HH
and should not be attempted.
9. #RESET connection to a V
HH
supply is allowed for a maximum cumulative period of 80 hours.
10. #BYTE input level is V
DD
±
0.2V in word mode or V
SS
±
0.2V in byte mode. #WP input level is V
DD
±
0.2V or V
SS
±
0.2V.
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