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參數資料
| 型號： | W312-02 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | FTG for VIA K7 Series Chipset with Programmable Output Frequency |
| 中文描述： | 威盛K7系列芯片組FTG具有可編程輸出頻率 |
| 文件頁數： | 18/21頁 |
| 文件大小： | 143K |
| 代理商： | W312-02 |
W312-02
Document #: 38-07259 Rev. *B
Page 18 of 21
PCI Clock Outputs (Lump Capacitance Test Load = 30 pF)
Parameter
Description
t
P
Period
t
H
High Time
t
L
Low Time
t
R
Output Rise Edge Rate
t
F
Output Fall Edge Rate
t
D
Duty Cycle
t
JC
Jitter, Cycle-to-Cycle
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
Measured on rising edge at 1.5V
Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
Average value during switching transition. Used for
determining series termination value.
Min.
30
12
12
1
1
45
Typ.
Max.
Unit
ns
ns
ns
V/ns
V/ns
%
ps
4
4
55
250
t
SK
t
O
Output Skew
CPU to PCI Clock Skew
500
4
ps
ns
1.5
f
ST
Frequency Stabilization
from Power-up (cold
start)
AC Output Impedance
3
ms
Z
o
30
REF Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
t
R
Output Rise Edge Rate
t
F
Output Fall Edge Rate
t
D
Duty Cycle
f
ST
Frequency Stabilization from
Power-up (cold start)
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition. Used
for determining series termination value.
Min.
Typ.
14.318
Max.
Unit
MHz
V/ns
V/ns
%
ms
0.5
0.5
45
2
2
55
3
Z
o
AC Output Impedance
40
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
f
D
Deviation from 48 MHz
m/n
PLL Ratio
t
R
Output Rise Edge Rate
t
F
Output Fall Edge Rate
t
D
Duty Cycle
f
ST
Frequency Stabilization
from Power-up (cold start)
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(48.008
–
48)/48
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
Average value during switching transition. Used
for determining series termination value.
Min.
Typ.
48.008
+167
57/17
Max.
Unit
MHz
ppm
0.5
0.5
45
2
2
V/ns
V/ns
%
ms
55
3
Z
o
AC Output Impedance
40
相關PDF資料 |
PDF描述 |
|---|---|
| W312-02H | FTG for VIA K7 Series Chipset with Programmable Output Frequency |
| W312-02HT | FTG for VIA K7 Series Chipset with Programmable Output Frequency |
| W320-04 | 200-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs |
| W320-04H | 200-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs |
| W320-04X | 200-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W312-02_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for VIA⑩ K7 Series Chipset with Programmable Output Frequency |
| W312-02H | 制造商:Rochester Electronics LLC 功能描述:PROGRAMMABLE OVERCLOCK SOLUTION FOR VIA KT266 - Bulk |
| W312-02HT | 制造商:Rochester Electronics LLC 功能描述:TIMING DEVICE - Bulk |
| W3120SMRC | 制造商:Winslow Adaptics Ltd 功能描述:20 way dual in line surface mount socket |
| W3120TRC | 制造商:Winslow Adaptics Ltd 功能描述:20way low profile DIL socket,0.3in pitch |
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